Table 901. Epr_Vd2 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Power Management Controller digital interface (PMC_dig)
Offset: PMC_BASE + 0x0020
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Field
0–30 Reserved.
LVD2_C low-voltage status flag—low voltage 0.98 V Core cold point supply.
31
0 Currently no occurrence, or previously cleared by writing '1'.
LVD2_C
1 LVD occurrence detected.
54.3.1.5 Event Pending register (EPR_VD3)
This register indicates the present and past state of the voltage detect signals. If the voltage
detect event crosses the trigger threshold after the last clearing event, the flag bit is set
asynchronously. Write '1' to clear the flag bit.
Offset: PMC_BASE + 0x0030
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
1578/2058
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 939. Event Pending register (EPR_VD2)

Table 901. EPR_VD2 field descriptions

2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 940. Event Pending register (EPR_VD3)
DocID027809 Rev 4
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
0 0 0 0
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0
w1c
0 0 0 0
RM0400
14 15
0 0
0 0
30 31
0
w1c
0 0
14 15
0 0
0 0
30 31
0 0
0 0