Handshaking With Processor - STMicroelectronics SPC572L series Reference Manual

RM0400
18.6.2.1.4 Comparator
The comparator logic compares the highest priority output from the associated priority
arbitrator subblock with PRI in the associated INTC_CPRn. If the comparator detects that
this highest priority is higher than the current priority, then it asserts the interrupt request to
the associated processor. This interrupt request to the processor asserts whether this
highest priority is raised above the value of PRI in the associated INTC_CPRn, or the PRI
value in the associated INTC_CPRn is lowered below this highest priority. This highest
priority then becomes the new priority which is written to PRI in the associated INTC_CPRn
when the interrupt request to the processor is acknowledged. Interrupt requests whose
PRIn in INTC_PSRn are zero will not cause a preemption because their PRIn will not be
higher than PRI in the associated INTC_CPRn.
Another function of the comparator is to signal an update of the INTC_IACKRn with the
vector number of the first interrupt that arrives that has a priority higher than the current
priority. Once the vector number and priority are captured, they cannot be superseded by a
higher priority interrupt until an update of the INTC_CPRn occurs. In software vector mode,
higher priority interrupts can supersede the previously captured interrupt vector number and
priority until the time a hardware or software interrupt acknowledge is processed.
18.6.2.2 Stack (LIFO)
The LIFO stores the preempted PRI values from the associated INTC_CPRn. Therefore,
because these priorities are stacked within the INTC, if interrupts need to be enabled during
the ISR, at the beginning of the interrupt exception handler the PRI value in the associated
INTC_CPRn does not need to be loaded from the associated INTC_CPRn and stored onto
the context stack. Likewise at the end of the interrupt exception handler, the priority does not
need to be loaded from the context stack and stored into the associated INTC_CPRn.
The PRI value in the associated INTC_CPRn is pushed onto the LIFO when the associated
INTC_IACKRn is read in software vector mode or the interrupt acknowledge signal from the
associated processor is asserted in hardware vector mode. The priority is popped into PRI
in the associated INTC_CPRn whenever the associated INTC_EOIRn is written. An
exception case in hardware vector mode to this behavior is described in
Hardware vector
Although the INTC supports up to 64 priorities, an ISR executing with PRI in the
INTC_CPRn equal to 15 will not be preempted. Therefore, the LIFO supports the stacking of
15 priorities. However, the LIFO is only 14 entries deep. An entry for a priority of 0 is not
needed because of the ways that pushing onto a full LIFO and popping an empty LIFO are
treated. If the LIFO is pushed 15 or more times than it is popped, the priorities first pushed
are overwritten. A priority of 0 would be an overwritten priority. However, the LIFO will pop
zeroes if it is popped more times than it is pushed. Therefore, although a priority of 0 was
overwritten, it is regenerated with the popping of an empty LIFO.
18.6.3

Handshaking with processor

18.6.3.1 Software vector mode handshaking
18.6.3.1.1 Acknowledging interrupt request to processor
The software vector mode handshaking can be used with processors that only support an
interrupt request to them, or processors that support both an interrupt request by itself as
well as an interrupt request with an interrupt vector. The software vector mode handshaking
mode.
DocID027809 Rev 4
Interrupt Controller (INTC)
Section 18.4.2,
369/2058
382