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LINFlexD
channels enabled. The correspondence between channel number and ID filter is based
on IFMI (identifier filter match index).
•
In LIN master mode both the DMA channels (TX and RX) must be enabled in case the
DMA capability is required.
•
In UART mode the DMA capability can be used only if the UART Tx/Rx buffers are
configured as FIFOs.
•
DMA and CPU operating modes are mutually exclusive for the data/frame transfer on a
UART or LIN node. Once a DMA transfer is finished the CPU can manage subsequent
accesses.
•
Error management must always be executed via the CPU enabling the related error
interrupt sources. DMA capability does not provide support for error management.
Error management means checking status bits, handling IRQs, and potentially
canceling DMA transfers.
•
The DMA programming model must be coherent with the TCD setting defined in this
document
•
When IPG_STOP is requested, SW has to first disable DMATXE/DMARXE channel
registers, after the current minor loop finishes (indicated by the clearing of ACTIVE bit
in DMA TCD register). This ensures that IPG_STOP_ACK is generated and IP enters
STOP mode.
50.4
Memory map and register description
50.4.1
Memory map
Table 825
Note:
In Master mode, the registers IFCR0 – IFCR15 are not present.
Note:
In Master Mode, read access to IFMI register and read/write access to IFER and IFMR
registers would result in ips_xfr_err being flagged.
Address offset
(hex)
00
04
08
0C
10
14
18
1C
20
24
28
1456/2058
shows the LINFlexD memory/register map.
Table 825. LINFlexD memory map
Register description
LIN Control register 1 (LINCR1)
LIN Interrupt Enable register (LINIER)
LIN Status register (LINSR)
LIN Error Status register (LINESR)
UART Mode Control register (UARTCR)
UART Mode Status register (UARTSR)
LIN Timeout Control Status register (LINTCSR)
LIN Output Compare register (LINOCR)
LIN Timeout Control register (LINTOCR)
LIN Fractional Baud Rate register (LINFBRR)
LIN Integer Baud Rate register (LINIBRR)
DocID027809 Rev 4
Register
Location
(1)
classification
Saf-Relv
on page 1458
Saf-Relv
on page 1460
No-Saf
on page 1463
No-Saf
on page 1466
Saf-Relv
on page 1468
No-Saf
on page 1472
Saf-Relv
on page 1474
Saf-Relv
on page 1475
Saf-Relv
on page 1476
Saf-Relv
on page 1477
Saf-Relv
on page 1478
RM0400
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