Overlay And Internal Trace Memory Full Status Generation - STMicroelectronics SPC572L series Reference Manual

RM0400
Timestamping is enabled by setting the TEN bit of the NAR_CR. This causes the NAR to
assert the time stamp enable signal to clients. Typically, the user would also set the TRS bit
at this time to reset the NAR Time stamp counter. Internally the NAR has a 30-bit counter
external to the NPC block. This 30-bit counter is broadcast to all clients after encoding its
value in Gray code. This minimizes the error in synchronization by the clients. The NPC
uses an additional internal 24-bit counter to send the timestamp inside its messages. The
client converts the gray coded timestamp to binary to append to the Nexus messages.
The Time stamp mode, a 2-bit field, is broadcasted to all client which tells the granularity of
sending time stamps into message. This is controlled by the TSG bits of the NAR_CR.
Asynchronous clients, those on a separate clock domain from the NAR, synchronize the
enable, mode and timestamp value in their domain. The error introduced by this is assumed
to be within tolerable range by application.
A timestamp counter reset can be forced by causing a 0 to 1 transition in the TRS bits of the
NAR_CR. The NAR deasserts the enable signal to clients while the reset occurs, and then
the counter is restarted (assuming the TEN bit is set). Data throughput can be increased (at
the loss of timestamp granularity) by controlling the TSG bits of the NAR_CR. Rather than
adding a timestamp to every message, clients can be told to only stamp every 4th, 16th, or
32nd message, easing the bandwidth requirements on the output ports.
The timestamp block maintains the timestamp counter for NAR. It is the central time source
for all synchronous/asynchronous clients.
65.5.12

Overlay and internal trace memory full status generation

In certain events, such as main memory (internal trace memory) full or external overlay
trace memory full, it is required to control the clients to stop sending data, to avoid any loss
of messages from the clients.
The NAR provides three outputs (triggers) to indicate three different situations as described
below:
•
Internal trace memory (the main queue) is full
•
External debug memory on trace memory bus is full
•
External debug memory on trace memory bus is full up to a programmable watermark
set by the configuration register
The last two triggers are used by SPU to generate stall and suppress triggers. Typically the
stall request should be generated whenever space in the external memory connected to
trace memory bus has been exhausted. The NAR starts writing from the first location (wrap)
as specified in trace memory bus address register in this condition if overwrite trace memory
bus debug memory (TBW bit) is set in the NAR_TCR.
The user should configure the partial full watermark register such that it can give around
90% full indication of external debug memory on the trace memory bus. The emulator tool
memory full indication is typically generated from the DCI block which actually
communicates with the tool.
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Nexus Aurora Router (NAR)
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