Figure 553. Write Transfer (Lfast Frame Encapsulation Is Not Shown) - STMicroelectronics SPC572L series Reference Manual

Serial Interprocessor Interface (SIPI)
MSB
Header
16 bits
*Same data allocation as for Register Read Transfer
Note: In the case of an 8-bit transfer, address bits [31:2] are used as address and bits [1:0] are
used as a byte enable.
–
In the case of a 16-bit transfer, address bits [31:1] are used as address and bit [0] is used as
a half-word enable.
–
45.7.3.2 Streaming write transfer
Streaming write transfers have 256 bits of payload.
45.7.3.2.1 Streaming write transfer with address
Settin the address is performed using a direct write transfer. SIPI_MAXCR and SIPI_ARR
are written before the SIPI_ACR. This is to ensure that the unwanted behavior of the SIPI
trying to access non-shared memory is avoided. This is only true for the very first streaming
command, subsequent streaming command(s) may not have the need to write
SIPI_MAXCR and SIPI_ARR (see <Cross Refs>Section 45.15.1.10, SIPI Max Count
Register (SIPI_MAXCR), <Cross Refs>Section 45.15.1.12, SIPI Address Count Register
(SIPI_ACR), and <Cross Refs>Section 45.15.1.11, SIPI Address Reload Register
(SIPI_ARR).
1104/2058

Figure 553. Write transfer (LFAST frame encapsulation is not shown)

Address
32 bits
Bits[1:0]:
– 00 – byte 3 enabled (MSB)
– 01 – byte 2 enabled
– 10 – byte 1 enabled
– 11 – byte 0 enabled (LSB)
Bit[0]:
– 0 – half-word 1 enabled (MSB)
– 1 – half-word 0 enabled (LSB)
DocID027809 Rev 4
8/16/32 bit data*
32 bits
96 bits
SIPI Frame
RM0400
Bit Stream Direction
LSB
CRC16
16 bits