Fec Frame Reception - STMicroelectronics SPC572L series Reference Manual

RM0400
fetched is already being processed internally (as a result of a wrap). As the FEC nears the
end of the transmission of one frame, it begins to DMA the data for the next frame. To
remain one BD ahead of the DMA, it also fetches the TxBD for the next frame. It is possible
that the FEC fetches from memory a BD that has already been processed but not yet written
back (it is read a second time with the R bit remains set). In this case, the data is fetched
and transmitted again.
Using at least three TxBDs fixes this problem for large frames, but not for small frames. To
ensure correct operation for large or small frames, one of the following must be true:
•
The FEC software driver ensures that there is always at least one TxBD with the ready
bit cleared.
•
Every frame uses more than one TxBD and every TxBD but the last is written back
immediately after the data is fetched.
•
The FEC software driver ensures a minimum frame size, n. The minimum number of
TxBDs is then (Tx FIFO Size ÷ (n + 4)) rounded up to the nearest integer (though the
result cannot be less than three). The default Tx FIFO size is 192 bytes; this size is
programmable.
48.5.10

FEC frame reception

The FEC receiver works with almost no intervention from the host and can perform address
recognition, CRC checking, short frame checking, and maximum frame length checking.
The Ethernet controller receives serial data lsb first.
When the driver enables the FEC receiver by setting ECR[ETHER_EN], it immediately
starts processing receive frames. When FEC_RXDV is asserted, the receiver first checks
for a valid PA/SFD header. If the PA/SFD is valid, it is stripped and the receiver processes
the frame. If a valid PA/SFD is not found, the frame is ignored.
In serial mode, the first 16 bit times of RX_D0 following assertion of FEC_RXDV are
ignored. Following the first 16 bit times, the data sequence is checked for alternating 1/0s. If
a 11 or 00 data sequence is detected during bit times 17 to 21, the remainder of the frame is
ignored. After bit time 21, the data sequence is monitored for a valid SFD (11). If a 00 is
detected, the frame is rejected. When a 11 is detected, the PA/SFD sequence is complete.
In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA
bytes may occur, but if a 00 bit sequence is detected prior to the SFD byte, the frame is
ignored.
After the first 6 bytes of the frame are received, the FEC performs address recognition on
the frame.
After a collision window (64 bytes) of data is received and if address recognition has not
rejected the frame, the receive FIFO signals the frame is accepted and may be passed on to
the DMA. If the frame is a runt (due to collision) or is rejected by address recognition, the
receive FIFO is notified to reject the frame. Therefore, no collision fragments are presented
to you except late collisions, which indicate serious LAN problems.
During reception, the Ethernet controller checks for various error conditions and after the
entire frame is written into the FIFO, a 32-bit frame status word is written into the FIFO. This
status word contains the M, BC, MC, LG, NO, CR, OV, and TR status bits, and the frame
length. See
Receive buffer (RXB) and frame interrupts (RFINT) may be generated if enabled by the
EIMR register. A receive error interrupt is a babbling receiver error (BABR). Receive frames
are not truncated if they exceed the max frame length (MAX_FL); however, the BABR
Section 48.5.19.2: Reception
DocID027809 Rev 4
Fast Ethernet Controller (FEC)
errors, for more details.
1349/2058
1358