Modes Of Operation - STMicroelectronics SPC572L series Reference Manual

GTM Development Interface (GTMDI)
42.3.2

Modes of operation

The GTMDI block is placed in reset when the Nexus reset signal is asserted. The JTAG
registers controlled by the TCK clock are also put into the reset state if the TAP controller is
in the TEST-LOGIC-RESET state. Holding TMS high for five consecutive rising edges of
TCK guarantees entry into the TEST-LOGIC-RESET state regardless of the initial TAP
controller state. Asserting the Nexus reset signal results in asynchronous entry into the reset
state not only of the TCK controlled registers but all registers in the GTMDI. The GTMDI is
unaffected by other sources of reset. While in reset, the following actions occur:
•
The TAP controller is forced into the TEST-LOGIC-RESET state
•
The auxiliary output port pins are negated
•
The auxiliary output port enable outputs are negated
•
The TDI, TMS, and TCK TAP inputs are ignored (The TMS and TCK signal are ignored
only while the Nexus reset signal is asserted.)
•
Registers default back to their reset values
Note: The GTMDI is not reset by the system reset signal. It is reset during device Power On reset
or by a dedicated Nexus reset thus preserving internal registers state and programming
during system reset.
Debug Mode can be controlled by on-chip logic through the system debug signal. The level
on this signal defines if the GTM module is in debug mode, meaning that it is in Halt state
and accepts write and read accesses to internal registers that do not modify the state of
those registers. If asserted, the GTM enters Halt state. If negated, the GTM debug mode is
controlled by other sources, internal to the GTMDI. The GTM may enter debug out of reset
by asserting the system debug signal while the device is being reset. By detecting this
condition, the GTMDI puts the GTM into the Halt state. The GDE and SDBE bits described
in Figure 407
42.3.3 DATA port
GTMDI messages are sent through the Message Data Bus. The Message Data Bus has a
fixed width of 32 bits which defines one BEAT of data. There are three BEATS per NAR
clock thus 96 bits are transmitted in parallel.
42.4 External signal description
The GTMDI pinout provides interface for the transmission of messages and for accessing
Nexus registers. The GTMDI pin definition is outlined in
876/2058
must be set during reset allowing the GTM to enter debug state.
DocID027809 Rev 4
Table 457.
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