STMicroelectronics SPC572L series Reference Manual page 642

Embedded Flash Memory (MP55)
As with Array Integrity Check, the internal MISR calculator is a 64 + 8 + 1-bit register. The
128-bit data, the corresponding ECC parity data and the double ECC (ERR) errors of the
four doublewords are therefore captured by the MISR through 2 different Read accesses at
the same location. The whole check is accomplished through 2 complete scans of the
memory address space:
1. The first pass scans only bits 63-0 + 8 ecc + ERR of each doubleword.
2. The second pass scans only bits 128-64 + 8 ecc + ERR of each doubleword.
The 128-bit data and the respective ECC parity data are sampled after any single-bit ECC
correction, and the double error flags are set after any ECC detection. Single-bit logging is
always enabled regardless of the value of UT0[SBCE], resulting in the MCR[SBC] flag and
related address to be captured in ADR reg, but this doesn't alter the final signature in the
UM0–9.
In any case, the charge losses detected through the Margin Read cannot be considered
device failures and no Failure Analysis is initiated on them.
The Margin Read Setup operation consists of the following sequence of events:
1. Set UTE in UT0 by writing the respective password in UT0.
2. Select the block(s) to be checked by writing 1's to the appropriate register(s) in SEL0,
SEL1 and SEL2 registers. Blocks selected for Margin Read do not need to be
unlocked. It is not possible to do Margin Read operations on the UTEST Nonvolatile
Memory block.
3. Seed the MISR UM0–9 with desired values.
4. Ensure that MCR[EER] and MCR[SBC] are cleared.
5. Set UT0[SBCE] to '1' to detect single bits during Margin Read.
6. Change the value of UT0[MRE] from '0' to '1'.
7. Select the Margin level: UT0[MRV]=0 for 0's margin, UT0[MRV]=1 for 1's margin.
8. Write a logic '1' to UT0[AIE] to start the Margin Read.
9. Wait until the UT0[AID] bit goes high.
10. Check that UT0[NAIBP] is set to '1' if breakpoints were previously enabled so that
MCR[EER], MCR[SBC] and ADR[ADDR] may be checked to determine the cause and
address of the break. Prior to resuming operation, clear MCR[SBC] or MCR[EER].
Operation may then be resumed by clearing UT0[NAIBP]. Continue to wait until
UT0[AID] goes high. If breakpoints were not enabled, or if UT0[NAIBP] is low when
UT0[AID] goes high, then the operation is complete.
11. Compare UM0–9 content with the expected results.
12. Check MCR[EER] and MCR[SBC].
13. Write a logic '0' to UT0[AIE], UT0[MRE] and UT0[MRV].
14. If more blocks are to be checked, return to step 2.
The linear address sequence is used regardless of the value of UT0[AIS].
Caution: Do not modify the content of Block Select (SEL0, SEL1, and SEL2) and Lock (LOCK0,
LOCK1, and LOCK2) registers during execution of the Margin Read operation, otherwise
the MISR value may vary unpredictably.
User mode array reads requested during the Margin Read are ignored to ensure that the
Margin Read operation is not corrupted. The memory array does not respond to array Read
requests during this time. User mode array reads may be executed if suspended or at a
breakpoint.
642/2058 DocID027809 Rev 4
RM0400