Clear Enable Error Interrupt Register (Dma_Ceei) - STMicroelectronics SPC572L series Reference Manual

Enhanced Direct Memory Access (eDMA)
Address: FC0A_0000 + 0x001A
0
R 0
W NOP
Reset 0
Figure 125. Set Enable Error Interrupt Register (DMA_SEEI)
Field
0 0Normal operation
NOP 1No operation, ignore bits 1–7 of this register
Sets all enable error interrupts
1
0Set only those EEI bits specified in the SEEI field.
SAEE
1Sets all bits in EEI
2–7 Set enable error interrupt
SEEI Sets the corresponding bit in EEIL
19.3.8

Clear Enable Error Interrupt Register (DMA_CEEI)

The Clear Enable Error Interrupt Register (DMA_CEEI) provides a simple memory-mapped
mechanism to clear a given bit in the EEIL to disable the error interrupt for a given channel.
The data value on a register write causes the corresponding bit in the EEIL to be cleared.
Setting the CAEE bit provides a global clear function, forcing the EEIL contents to be
cleared, disabling all DMA request inputs.
If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers
as a 32-bit word. Reads of this register return all zeroes.
Address: FC0A_0000 + 0x001B
0
R 0
W NOP
Reset 0
Figure 126. Clear Enable Error Interrupt Register (DMA_CEEI)
Field
0 0Normal operation
NOP 1No operation, ignore bits 1–7 of this register
Clear all enable error interrupts
1
0Clear only those EEI bits specified in the CEEI field
CAEE
1Clear all bits in EEI
2–7 Clear enable error interrupt
CEEI Clears the corresponding bit in EEIL
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1 2
0
SAEE
0 0
Table 171. DMA_SEEI field descriptions
1 2
0
CAEE
0 0
Table 172. DMA_CEEI field descriptions
DocID027809 Rev 4
3 4
0
SEEI
0 0
Description
3 4
0
CEEI
0 0
Description
Access: User write-only
5 6
0 0
Access: User write-only
5 6
0 0
RM0400
7
0
7
0