Table 474. Gtmdi_Dpll_Wpc3 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Table 473. GTMDI_DPLL_WPC2 field descriptions(Continued)
Field
Watchpoint Trigger Enable 2. The TEN2 field controls if a watchpoint external trigger is issued by
1 the DPLL RAM selected access.
TEN2 0 Disable External Watchpoint Trigger Generation
1 Enable External Watchpoint Trigger Generation
Start/Stop Enable 2. The SEN2 bit field enable the DPLL RAM selected access event to consider
the Start/Stop inputs for watchpoint trace message generation. If this bit is cleared, the messages
0
are controlled only by JTAG writes to the WMC1 field in the GTMDI_DPLL_WPC1 register.
SEN2
0 Disable trace control from Start/Stop inputs
1 Enable trace control from Start/Stop inputs
42.5.1.16 DPLL watchpoint control 3 register (GTMDI_DPLL_WPC3)
The GTMDI_DPLL_WPC3 register shown in
the selected DPLL RAM access. A match to this value causes a Watchpoint.
Register index: 43
31 30
R 0 0
W
RESET: 0 0
15 14
R
W
RESET: 0 0
Figure 421. DPLL watchpoint control 3 register (GTMDI_DPLL_WPC3)
Table 474
Field
Data Mask. The DMASK field is a mask for the data comparator. If set, the data read or written to
28 the memory should not be considered for watchpoint generation.
DMASK 0 RAM_DATA should be compared with data from RAM access
1 RAM_DATA is masked and should not be compared
23–0
Data value. The RAM_DATA[23:0] field defines the data value that is compared against the data
accessed from the selected DPLL RAM.
RAM_DATA
42.5.1.17 DPLL watchpoint control 4 register (GTMDI_DPLL_WPC4)
The GTMDI_DPLL_WPC4 register shown in
the DPLL selected RAM address comparison.
29 28 27 26
0 0
DMASK
0 0 0
13 12 11 10
0 0 0
describes the GTMDI_DPLL_WPC3 register functions.

Table 474. GTMDI_DPLL_WPC3 field descriptions

DocID027809 Rev 4
GTM Development Interface (GTMDI)
Description
Figure 421
25 24 23
0 0 0
0 0 0 0
9 8 7
RAM_DATA[15:0]
0 0 0 0
Description
Figure 422
defines the data value observed in
22 21 20 19
RAM_DATA[23:16]
0 0 0 0
6 5 4 3
0 0 0 0
defines the RAM address mask for
18 17 16
0 0 0
2 1 0
0 0 0
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960