Figure 1100.Complex Sequence Example - STMicroelectronics SPC572L series Reference Manual

Sequence Processing Unit (SPU)
SEQUENCE n
63.6.4.2 Typical sequence example
For this example, the user would like to create a timestamp in the trace stream each time a
function is entered and stop the trace signal on the 12th occurance of the function. This use
case can be implemented as follows:
•
State 0 takes an instruction address compare as its input. On a match of the instruction
address to a specific function, called function_x, the sequence moves to State 1. Upon
this action, State0 is configured to insert a timestamp into the trace stream and also
increment an SPU counter, say counter[0].
•
The sequence is now in State 1. State 1 takes an input from counter[0]. Counter[0] has
been pre-configured to create a match event when the counter value is equal to 12.
–
–
63.6.4.3 Sequence status register description
A status register providing feedback on each sequence is provided to allow debug tools to
identify the source of a debug event from the SPU. The status register consists of two field
types:
•
States—each state has a sticky bit that is set upon a true match of the state logic. This
sticky bit is cleared upon a write to this register.
•
Sequence status—each sequence has a field indicating the active state of the state
machine. This is a read only field.
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Figure 1100. Complex sequence example
FALSE
TRUE
STATE 0
FALSE
TRUE
STATE 4
If the value of counter[0] is less than 12, then the sequence moves back to State0.
If the value of couner[0] is equal to 12, then the sequence completes and an action
from State1 disables the trace signal.
STATE 1
FALSE
TRUE
DocID027809 Rev 4
FALSE
STATE 2
TRUE
TRUE
STATE 3
RM0400
FALSE