STMicroelectronics SPC572L series Reference Manual page 977

RM0400
Offset
Interrupt force register
0x28048
(DPLL_IRQ_FORCINT)
0x2804C Interrupt mode register (DPLL_IRQ_MODE)
Error Interrupt enable register
0x28050
(DPLL_EIRQ_EN)
0x28054 – 0x280AC
Counter for pulses for TBU_TS1 to be sent in
0x280B0
automatic end mode (DPLL_INC_CNT1)
Counter for pulses for TBU_TS2 to be sent in
0x280B4 automatic end mode when
SMC = RMO = 1w (DPLL_INC_CNT2)
Old RAM pointer and offset value for
0x280B8
TRIGGER (DPLL_APT_SYNC)
Old RAM pointer and offset value for STATE
0x280BC
(DPLL_APS_SYNC)
TBU_TS0 value at last TRIGGER event
0x280C0
(DPLL_TBU_TS0_T)
TBU_TS0 value at last STATE event
0x280C4
(DPLL_TBU_TS0_S)
Direct load input value for SUB_INC1
0x280C8
(DPLL_ADD_IN_LD1)
Direct load input value for SUB_INC2
0x280CC
(DPLL_ADD_IN_LD2)
0x280D0 – 0x280F8
0x280FC Status Register (DPLL_STATUS)
9 bit ID information for input signal PMTR_n
0x28100 + n*0x0004
(8:0), n = 0...31 (DPLL_ID_PMTR_n)
0x28180 – 0x281DC
shadow register of DPLL_CTRL_0
0x281E0
(DPLL_CTRL_0_SHADOW_TRIGGER)
shadow register of DPLL_CTRL_0
0x281E4
(DPLL_CTRL_0_SHADOW_STATE)
shadow register of DPLL_CTRL_1
0x281E8
(DPLL_CTRL_1_SHADOW_TRIGGER)
shadow register of DPLL_CTRL_1
0x281EC
(DPLL_CTRL_1_SHADOW_STATE)
0x281F0 – 0x281F8
Initialization Control and Status for RAMs
0x281FC
(DPLL_RAM_INI)
Table 516. GTMINT module memory map(Continued)
Use
DPLL RAM 1A Map
DocID027809 Rev 4
GTM101 Integration (GTMINT) Module
Access Reset value
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
Reserved
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
Reserved for DPLL
R/W 0x0000_0000
R/W 0x0000_01FE
Reserved for DPLL
R/W 0x0000_0257
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
Reserved
R/W 0x0000_0000
(1)
Location
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
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