Figure 1080.L2Nsel3 Register Format - STMicroelectronics SPC572L series Reference Manual

RM0400
Table 1021. L2nSEL2 register field descriptions(Continued)
Field
Third AND Gate Input 2 Selection.
000000No Input is selected (tie to 1'b1)
000001Level1 MUX 0 output
13–8
000010Level1 MUX 1 output
ThirdANDInput2 000011Level1 MUX 2 output
...
111110Level1 MUX 61 output
111111Level1 MUX 62 output
15–14 Reserved. Read returns 0.
Third AND Gate Input 3 Selection.
000000No Input is selected (tie to 1'b1)
000001Level1 MUX 0 output
21–16
000010Level1 MUX 1 output
ThirdANDInput3 000011Level1 MUX 2 output
...
111110Level1 MUX 61 output
111111Level1 MUX 62 output
23–22 Reserved. Read returns 0.
Third AND Gate Input 4 Selection.
000000No Input is selected (tie to 1'b1)
000001Level1 MUX 0 output
29–24
000010Level1 MUX 1 output
ThirdANDInput4 000011Level1 MUX 2 output
...
111110Level1 MUX 61 output
111111Level1 MUX 62 output
31–30 Reserved. Read returns 0.
63.5.1.2.4 Level2 Mux state n selection 3 (L2nSEL3)
Figure 1080
0x1A (State0)
0x1E (State1)
0x22 (State2)
Offset 0x26 (State3)
0x2A (State4)
0x2E (State5)
0x32 (State6)
0x36 (State7)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0
FourthANDInput4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
shows the format of the L2nSEL3 register where the state number, n = 0–7.
0 0
FourthANDInput3
Figure 1080. L2nSEL3 register format
DocID027809 Rev 4
Sequence Processing Unit (SPU)
Description
0 0
FourthANDInput2
Access: User read/write
8 7 6 5 4 3 2 1
0 0
FourthANDInput1
1835/2058
0
1863