Table 527. Endian Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
44.3.5.2.2 Endian Register (ENDN)
Address: 0x0004
0 1
R
W
Reset
16 17 18
R
W
Reset
Field
0:31 Endianness Test Value
ETV The endianness test value is 0x87654321.
44.3.5.2.3 Fast Bit Timing and Prescaler Register (FBTP)
This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time
may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be
programmed in the range of 1 to 1024 M_CAN clock periods. tq = (FBRP + 1) M_CAN clock
period.
FTSEG1 is the sum of Prop_Seg and Phase_Seg1. FTSEG2 is Phase_Seg2.
Therefore the length of the bit time is (prog rammed values) [FTSEG1 + FTSEG2 + 3] tq or
(functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq.
The Information Processing Time (IPT) is zero, meaning the data for the next bit is available
at the first clock edge after the sample point.
Address: 0x000C
0 1
R
TDCO
W
Reset 0 0
16 17 18
R 0 0
W
Reset 0 0
1. These are protected write (P) bits which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0
[INIT] of CCCR register are set to "1".
2 3 4 5
19 20 21
Figure 473. Endian Register

Table 527. Endian Register Field Descriptions

2 3 4 5
0
1 1
TDC
0 0 0 0
19 20 21
0 0
FTSEG
0 0 1 0
Figure 474. Fast Bit Timing and Prescaler Register
6 7 8 9
ETV
0x8765
22 23 24 25
ETV
0x4321
Description
6 7 8 9
0 0 0 0
22 23 24 25
0
1
1 0 0 0
DocID027809 Rev 4
CAN Subsystem
10 11 12
26 27 28
Access: Read Protected
10 11 12
(1)
FBRP
0 0 0
26 27 28
0
1
FTSEG2
1 1 0
Access: Read
13 14 15
29 30 31
13 14 15
0 0 0
29 30 31
1
FSJW
0 1 1
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