Figure 799. Slow Serial Message Dma Read Logic - STMicroelectronics SPC572L series Reference Manual

RM0400
Channel 6
Channel 7
Empty
Note: The arrows in the figure indicate next DMA transfer. One DMA Read Register set (3 registers) will be read in one transfer.
The formats in which the 3 types of Serial Messages will be stored in the buffers are shown
in figures below.
31 1
CH NUM
P
[3:0]
31 1
CH NUM
P
[3:0]
Figure 800
bit CFG (as shown in
(DMA_SMSG_BIT3)
figure) or bit TYPE (shown in
Register (DMA_SMSG_BIT3)
serial message. CRC, ID and Data fields are stored in format as received and shown in SAE
specification with just one exception that CRC is shifted to align with 16-bit boundary.

Figure 799. Slow Serial Message DMA read logic

Slow serial message DMA
Channel 4
Channel 5
Empty
CRC [5:0]
TIME STAMP [31:0]
Figure 800. Enhanced Serial Message with 8-bit ID field
CRC [5:0]
TIME STAMP [31:0]
Figure 801. Enhanced Serial Message with 4-bit ID field
and Figure 801 shows the enhanced serial messages. Bit C (shown in figure) or
Section 49.3.2.15: DMA Slow Serial Message Bit3 Read Register
description) defines the type of enhanced packet and bit P (shown in
Section 49.3.2.15: DMA Slow Serial Message Bit3 Read
description) defines whether it is short serial or enhanced
DocID027809 Rev 4
read register
Channel 2
Channel 3
DMA is
disabled
16 15
0 C
16 15
0 C
SENT Receiver (SRX)
Channel 1
0
ID [7:4] 0
Data Field [11:0]
1
ID [3:0] 0 Data [15:12] 0
Data Field [11:0]
Channel 0
0
ID [3:0] 0
0
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