Table 335. Error Injection Channel Enable Register (Eichen) Field Description - STMicroelectronics SPC572L series Reference Manual

RM0400

Table 335. Error Injection Channel Enable register (EICHEN) field description

Name
31
EICH0EN
30
EICH1EN
29
EICH2EN
28
EICH3EN
Error Injection Channel 0 Enable.
This bit enables the corresponding error injection channel. There is global error injection
enable (EIMCR[GEIEN]) also that must be asserted to enable error injection. Once error
injection is enabled, all subsequent read accesses will incur bit inversion(s) as defined in
Error Injection Descriptor0 registers (EICHD0) until the error injection channel is manually
disabled via software.
Any write to the corresponding EICHDn registers clears the corresponding
EICHEN[EICHnEN] bit, leaving the error injection channel disabled. This bit is cleared by
power-on reset and unaffected by other types of system reset.
0 Error injection is disabled on Error Injector Channel0
1 Error injection is enabled on Error Injector Channel0
Error Injection Channel 1 Enable.
This bit enables the corresponding error injection channel. There is a global error injection
enable (EIMCR[GEIEN]) also that must be asserted to enable error injection. Once error
injection is enabled, all subsequent read accesses will incur bit inversion(s) as defined in
Error Injection Descriptor1 registers (EICHD1) until the error injection channel is manually
disabled via software.
Any write to the corresponding EICHDn registers clears the corresponding
EICHEN[EICHnEN] bit, leaving the error injection channel disabled. This bit is cleared by
power-on reset and unaffected by other types of system reset.
0 Error injection is disabled on Error Injector Channel1
1 Error injection is enabled on Error Injector Channel1
Error Injection Channel 2 Enable.
This bit enables the corresponding error injection channel. There is a global error injection
enable (EIMCR[GEIEN]) also that must be asserted to enable error injection. Once error
injection is enabled, all subsequent read accesses will incur bit inversion(s) as defined in
Error Injection Descriptor2 registers (EICHD2) until the error injection channel is manually
disabled via software.
Any write to the corresponding EICHDn registers clears the corresponding
EICHEN[EICHnEN] bit, leaving the error injection channel disabled. This bit is cleared by
power-on reset and unaffected by other types of system reset.
0 Error injection is disabled on Error Injector Channel 2
1 Error injection is enabled on Error Injector Channel 2
Error Injection Channel 3 Enable.
This bit enables the corresponding error injection channel. There is a global error injection
enable (EIMCR[GEIEN]) also that must be asserted to enable error injection. Once error
injection is enabled, all subsequent read accesses will incur bit inversion(s) as defined in
Error Injection Descriptor3 registers (EICHD3) until the error injection channel is manually
disabled via software.
Any write to the corresponding EICHDn registers clears the corresponding
EICHEN[EICHnEN] bit, leaving the error injection channel disabled. This bit is cleared by
power-on reset and unaffected by other types of system reset.
0 Error injection is disabled on Error Injector Channel 3
1 Error injection is enabled on Error Injector Channel 3
DocID027809 Rev 4
Error Injection Module (EIM)
Description
687/2058
691