Enable Request Register Low (Dma_Erql) - STMicroelectronics SPC572L series Reference Manual

Enhanced Direct Memory Access (eDMA)
Field
Channel priority error
17
0 No channel priority error
CPE 1 The last recorded error was a configuration error in the channel priorities. Channel priorities are
not unique.
18–23
Error channel number and/or last recorded error cancelled transfer
ERRCHN
Source address error
24
0 No source address configuration error.
SAE 1 The last recorded error was a configuration error detected in the TCDn_SADDR field.
TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]
Source offset error
25
0 No source offset configuration error
SOE 1 The last recorded error was a configuration error detected in the TCDn_SOFF field.
TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
Destination address error
26
0 No destination address configuration error
DAE 1 The last recorded error was a configuration error detected in the TCDn_DADDR field.
TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
Destination offset error
27
0 No destination offset configuration error
DOE 1 The last recorded error was a configuration error detected in the TCDn_DOFF field.
TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
NBYTES/CITER configuration error
28
0 No NBYTES/CITER configuration error
NCE 1 The last recorded error was a configuration error detected in the TCDn_NBYTES or
TCDn_CITER fields.
Scatter/gather configuration error
0 No scatter/gather configuration error
29
1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This
SGE
field is checked at the beginning of a scatter/gather operation after major loop completion if
TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32-byte boundary.
Source bus error
30
0 No source bus error
SBE
1 The last recorded error was a bus error on a source read
Destination bus error
31
0 No destination bus error
DBE
1 The last recorded error was a bus error on a destination write
19.3.3

Enable Request Register Low (DMA_ERQL)

The ERQL registers provide a bit map for the 16 implemented channels to enable the
request signal for each channel. EQRL covers channels 15–00.
The state of any given channel enable is directly affected by writes to this register; it is also
affected by writes to the SERQ and CERQ. The {S,C}ERQ registers are provided so the
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Table 166. DMA_ES field descriptions(Continued)
DocID027809 Rev 4
Description
RM0400