Buffer Descriptors - STMicroelectronics SPC572L series Reference Manual

Fast Ethernet Controller (FEC)
Table 779. MII management frame components(Continued)
Component
Five-bit field that allows for 32 registers to be addressed within each PHY. The first register bit
<regad>
transmitted is the MSB of the address.
Two-bit field that provides spacing between the register address field and the data field to
<ta>
avoid contention on the MDIO signal during a read operation.
<data> 16-bit data field. Bit 15 is the first data bit transmitted and received.
<idle> Idle condition (MDIO is in the high-impedance state).
The MII management register set located in the PHY may consist of a basic register set and
an extended register set as defined in
Register address
48.5.3

Buffer descriptors

This section provides a description of the operation of the driver/DMA via the buffer
descriptors. It is followed by a detailed description of the receive and transmit descriptor
fields.
48.5.3.1 Driver/DMA operation with buffer descriptors
The data for the FEC frames resides in one or more memory buffers external to the FEC.
Associated with each buffer is a buffer descriptor (BD), which contains a starting address
(32-bit aligned pointer), data length, and status/control information (which contains the
current state for the buffer). To permit maximum user flexibility, the BDs are also located in
external memory and are read by the FEC DMA engine.
Software produces buffers by allocating/initializing memory and initializing buffer
descriptors. Setting the RxBD[E] or TxBD[R] bit produces the buffer. Software writing to
TDAR or RDAR tells the FEC that a buffer is placed in external memory for the transmit or
receive data traffic, respectively. The hardware reads the BDs and consumes the buffers
after they have been produced. After the data DMA is complete and the DMA engine writes
the buffer descriptor status bits, hardware clears RxBD[E] or TxBD[R] to signal the buffer
has been consumed. Software may poll the BDs to detect when the buffers are consumed
1340/2058
Table 780. MII management register set
0
1
2–3
4 Auto-negotiation advertisement
5
6
7
8–15
16–31
DocID027809 Rev 4
Description
Table 780.
Register name
Control
Status
PHY identifier
AN link partner ability
AN expansion
AN next page transmit
Reserved
Vendor-specific
RM0400
Register set
Basic
Extended