Figure 561. Sipi Single Register Read Api - STMicroelectronics SPC572L series Reference Manual

Serial Interprocessor Interface (SIPI)
TC / DMA
2. Step: Write channel data
Last Step: Read return value
1. Step: Set channel control
3. Step: Write channel address
4. Step: Read Status
Interrupt generation option
For Single Read Transfer Request generation
1. Software/DMA will configure SIPI_CCRn and SIPI_CDRn, with the last step by writing
SIPI_CARn.
2. As soon as SIPI_CAR is written, the initiator SIPI will calculate CRC of the header and
address fields and start transmitting data to the LFAST.
3. Software should poll SIPI_CSRn to determine when the request has completed. If
SIPI_CSRn[RAR] = 1, and interrupt will be generated (if SIPI_CIRn[RAIE] = 1). If
SIPI_CSRn[RAR] does not set then SIPI_ERR[TOEn] = 1, which indicates a timeout
has occured.
4. If SIPI_CSRn[RAR] = 1, then software can read the data register, or can take other
necessary action if SIPI_CSRn[RAR] = 0.
On Single Read transfer request reception
1. Target node will place the address and control information on its AHB Master Interface.
2. When the process in completed, target node will send read response back to LFAST.
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Figure 561. SIPI Single Register Read API

Channel x of SIPI Module
Single Read Transfer Address
(Figure
DocID027809 Rev 4
32 bits
Single Read Transfer Value
Transfer Read Configuration
Acknowledge Headers
Channel Status
Channel Error
Time Out
(Figure 561):
561):
RM0400