STMicroelectronics SPC572L series Reference Manual page 562

Flash memory controller (PFLASH Controller)
Field
19–23
RWSC
25
P0_DPFEN
27
P0_IPFEN
562/2058
Table 284. PFCR1 field descriptions(Continued)
Read Wait State Control. This field controls the number of wait-states to be added to the
best-case flash array access time for reads. The best-case flash array access time for
reads is one cycle.
This field must be set to a value corresponding to the operating frequency of the flash
memory controller and the actual read access time of the flash memory controller. The
required settings are documented in the SoC specification. Higher operating frequencies
require non-zero settings for this field for proper flash operation.
Shown below are the maximum operating frequencies for legal RWSC settings based on
specified access times at 150C. The integrator is strongly encourage to verify these
settings based on actual silicon results.
RWSC=0: 0MHz < fsys < 29.4MHz
RWSC=1: 29.4MHz < fsys < 58.8MHz
RWSC=2: 58.8MHz < fsys < 88.2MHz
RWSC=3: 88.2MHz < fsys < 117.6MHz
RWSC=4: 117.6MHz < fsys < 147.0MHz
RWSC=5: 147.0MHz < fsys < 176.5MHz
RWSC=6: 176.5MHz < fsys < 205.9MHz
RWSC=7: 205.9MHz < fsys < 235.5MHz
This field is set to 5'b00110 by hardware reset.
This field applies to the configuration of Port0 and Port1.
00000 No additional wait-states are added
00001 One additional wait-state is added
...
11111 Thirty-one additional wait-states are added
Port0 Data Prefetch Enable. This field enables or disables prefetching initiated by a data
read access. This field is cleared by hardware reset.
0 No prefetching is triggered by a data read access
1 Prefetching may be triggered by any data read access
Port0 Instruction Prefetch Enable. This bit enables or disables prefetching initiated by an
instruction read access. This field is cleared by hardware reset.
0 No prefetching is triggered by an instruction read access
1 Prefetching may be triggered by any instruction read access
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Description
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