External Debug Support - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Core Debug Support
Independent limit checks for supervisor and user accesses may be implemented by
allocating independent DACn resources to each, or a single limit may be applied using a
single DACn resource. Typically, a DAC1,2 pair operating in exclusive address range mode
is utilized for stack limit checking for a single shared limit. For separate limits, DAC3,4 may
also be utilized. If more than one DACn resource is utilized, a DAC hit on any resource
utilized for stack limit checking will cause the corresponding stack limit exception action to
occur. If both a hardware-owned and a software-owned resource generate a stack limit
exception for a given load or store, the software resource will have priority, since it is
detected prior to completion of the access, and the access is aborted, thus the hardware
event will not occur.
Enabling of this functionality is described in more detail in the description of the DACnCFG
fields in Table 942
Note that for DAC1 and DAC2, access type (read, write) control is part of DBCR0.
57.5

External debug support

External debug support is supplied through the OnCE controller serial interface, which
allows access to internal CPU registers and other system state while the CPU is halted in
debug mode. All debug resources including DBCR0–8, DBSR, IAC1–8, DAC1–4, and
DVC1–2 are accessible through the serial OnCE interface in external debug mode. Setting
the EDBCR0
mode, and unless otherwise permitted by the settings in EDBRAC0, disables software
updates to the debug control registers. When EDBCR0
set respective status bits will also cause the CPU to enter Debug mode if the event is not
masked in EDBSRMSK0, as opposed to generating Debug Interrupts, unless the specific
events are allocated to software via the settings in EDBRAC0. In Debug mode, the CPU is
halted at a recoverable boundary, and an external Debug Control Module may control CPU
operation through the On-Chip Emulation logic (OnCE).
Note that the descriptions of events in the subsections of
events and exceptions
owned by hardware, the events for those resources set the respective status bits in
EDBSR0 instead of DBSR.
Note: On the initial setting of EDBCR0
EDBCR0
through the OnCE interface. The CPU should be placed into debug mode via the OCR
control bit prior to writing EDM to '1'. This gives the debugger the opportunity to cleanly write
to the DBCRx registers and the DBSR to clear out any residual state / control information
that could cause unintended operation.
Note: It is intended for the CPU to remain in external debug mode (EDBCR0
single step or perform other debug mode entry/ reentry via the OCR
go+noexit commands, or by assertion of the jd_de_b signal.
Note: EDBCR0
regardless of whether it is set or cleared. This means that if EDBCR0
set, and then jd_en_once is negated (this should not occur), entry into debug mode will be
blocked, and all hardware debug events are blocked. Watchpoints are not blocked.
Due to clock domain design, the CPU clock (m_clk) must be active in order to perform
writes to debug registers other than the OnCE Command register (OCMD), the OnCE
Control register (OCR), External Debug Control Register 0 (EDBCR0), External Debug
1688/2058
and Table 945
/DBCR0 bit to '1' through the OnCE interface enables external debug
EDM EDM
refer to setting DBSR status bits, however, when resources are
has been set, all debug register resources may be subsequently controlled
EDM
operation will be blocked if OnCE operation is disabled (jd_en_once negated)
EDM
DocID027809 Rev 4
in Section 57.3.2, Debug Control and Status
to '1', other bits in DBCR0 will remain unchanged. After
EDM
is set, debug events enabled to
EDM
Section 57.2, Software debug
=1) in order to
EDM
, by performing
DR
was previously
EDM
RM0400
registers.
DR