Cpu Status And Control Scan Chain Register (Cpuscr) - STMicroelectronics SPC572L series Reference Manual

RM0400
is true), and EDBCR0
the 'bkpt' pseudo-instruction has entered the instruction register.
57.5.8.6 Debug notify halt instructions
The e_dnh and se_dnh instructions allow software to transition the core from a running
state to a debug halted state if enabled by EDBCR0
debugger with bits reserved in the instruction itself to pass additional information. Entry into
debug mode is not conditioned on EDBCR0
handlers as well as other software. For e200z215An3, when the CPU enters a debug halted
state due to a e_dnh or se_dnh instruction, the instruction will be stored in the CPUSCR[IR]
portion, and the CPUSCR[PC] value will point to the instruction. The external debugger
should update the CPUSCR prior to exiting the debug halted state to point past the e_dnh
or se_dnh instruction.
57.5.9

CPU Status and Control Scan Chain Register (CPUSCR)

A number of on-chip registers store the CPU pipeline status and are configured in a single
scan chain for access by the OnCE controller. The CPUSCR register contains these
processor resources, which are used to restore the pipeline and resume normal chip activity
upon return from the debug mode, as well as a mechanism for the emulator software to
access processor and memory contents.
pipeline information registers contained in the CPUSCR. Once debug mode has been
entered, it is required to scan in and update this register prior to exiting debug mode.
=1, the CPU enters the debug mode after the instruction following
EDM
Figure 1011
DocID027809 Rev 4
e200z215An3 Core Debug Support
, and provide the external
DNH_EN
, allowing for debug of software debug
EDM
shows the block diagram of the
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