Initialization/Application Information - STMicroelectronics SPC572L series Reference Manual

Enhanced Direct Memory Access (eDMA)
For an SRAM to internal peripheral bus transfer,
Equation 2 PEAKreq = 150 MHz / [ 4 + (1 + 0) + (1 + 1) + 3 ] cycles = 15.0 Mreq/s
For an internal peripheral bus-to-SRAM transfer,
Equation 3 PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 0) + 3 ] cycles = 15.0 Mreq/s
The minimum number of cycles to perform a single read/write, with zero wait states on the
system bus, from a cold start (where no channel is executing and the eDMA is idle):
•
11 cycles for a software (TCDn_CSR[START] bit) request
•
12 cycles for a hardware (eDMA peripheral request signal) request
Two cycles account for the arbitration pipeline and one extra cycle on the hardware request
resulting from the internal registering of the eDMA peripheral request signals. For the peak
request rate calculations above, the arbitration and request registering are absorbed in or
overlap the previous executing channel.
When channel linking or scatter/gather is enabled, a two cycle delay is imposed on the next
channel selection and startup. This allows the link channel or the scatter/gather channel to
be eligible and considered in the arbitration pool for next channel selection.
19.5

Initialization/application information

The following sections discuss initialization of the eDMA and programming considerations.
19.5.1 eDMA initialization
A typical initialization of the eDMA has the following sequence:
1. Write the CR register if a configuration other than the default is desired.
2. Write the channel priority levels into the DCHPRIn registers if a configuration other than
the default is desired.
3. Enable error interrupts in the EEI registers if so desired.
4. Write the 32-byte TCD for each channel that may request service.
5. Enable any hardware service requests via the ERQ register.
6. Request channel service by software (setting the TCDn_CSR[START] bit) or hardware
(slave device asserting its eDMA peripheral request signal).
After any channel requests service, a channel is selected for execution based on the
arbitration and priority levels written into the programmer's model. The eDMA engine reads
the entire TCD, including the TCD control and status fields (shown in
selected channel into its internal address path module. As the TCD is read, the first transfer
is initiated on the internal bus unless a configuration error is detected. Transfers from the
source (as defined by the source address, TCDn_SADDR) to the destination (as defined by
the destination address, TCDn_DADDR) continue until the specified number of bytes
(TCDn_NBYTES) are transferred. When the transfer is complete, the eDMA engine's local
TCDn_SADDR, TCDn_DADDR, and TCDn_CITER are written back to the main TCD
memory and any minor loop channel linking is performed, if enabled. If the major loop is
exhausted, further post processing executes (interrupts, major loop channel linking, and
scatter/gather operations) if enabled.
438/2058 DocID027809 Rev 4
RM0400
Table 198) for the