Interrupt Mask Register (Eimr) - STMicroelectronics SPC572L series Reference Manual

Fast Ethernet Controller (FEC)
Field
Collision retry limit. Indicates a collision occurred on each of 16 successive attempts to transmit the
RL frame. The frame is discarded without being transmitted and transmission of the next frame
commences. This error can only occur in half duplex mode.
Transmit FIFO underrun. Indicates the transmit FIFO became empty before the complete frame
UN was transmitted. A bad CRC is appended to the frame fragment and the remainder of the frame is
discarded.
48.4.2

Interrupt Mask Register (EIMR)

The EIMR controls which interrupt events are allowed to generate actual interrupts. A
hardware reset clears this register. If the corresponding bits in the EIR and EIMR registers
are set, an interrupt is generated. The interrupt signal remains asserted until a 1 is written to
the EIR bit (write 1 to clear) or a 0 is written to the EIMR bit.
Each bit in this register corresponds to an interrupt source defined by the EIR. The
corresponding EIMR bit determines whether an interrupt condition can generate an
interrupt. At every processor clock, the EIR samples the signal generated by the interrupting
source. The corresponding EIR bit reflects the state of the interrupt signal even if the
corresponding EIMR bit is set.
Offset: 008h
0 1
R
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Field
Heartbeat error interrupt mask.
HBERR
0 The interrupt source is masked.
1 The interrupt source is not masked.
Babbling receive error interrupt mask.
BABR
0 The interrupt source is masked.
1 The interrupt source is not masked.
Babbling transmit error interrupt mask.
BABT
0 The interrupt source is masked.
1 The interrupt source is not masked.
1304/2058
Table 699. EIR field descriptions(Continued)
2 3 4 5
GRA TXF TXB RXF RXB
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 691. Ethernet Interrupt Mask Register (EIMR)
Table 700. EIMR field descriptions
DocID027809 Rev 4
Description
6 7 8 9
MII
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Description
Access: User read/write
10 11 12 13
0
LC RL UN
0 0 0 0
26 27 28 29
0 0 0 0
0 0 0 0
RM0400
14 15
0 0
0 0
30 31
0 0
0 0