Figure 676. Rx Loopback Mode - STMicroelectronics SPC572L series Reference Manual

RM0400 LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
RXDATA_P
LR
RXDATA_N
TMCR[LPMOD]= RX LOOPBACK
TXDATA_P
LD
TXDATA_N
Entry to Rx Loopback mode:
1. S/W programs TMCR[LPMOD] = 000b.
2. Loopback can be turned on by either of the following methods:
–
–
Exit from Rx Loopback mode can be done by any of the following methods:
•
S/W programs TMCR[LPON] = 0
•
For LFAST Slave: - Transmission of ICLC Frame with payload 38h (Test mode off),
from LFAST Master
The peer LFAST device is required to maintain at least 2-bit IFG between two Loopback
frames in this mode.
47.7.7.1.2 Rx LVDS LoopBack mode
This loopback mode is provided to verify and characterize the LVDS pads. In this loopback
mode the data received by LFAST on Rx LVDS input is loopback to Tx LVDS output,
bypassing LFAST. For LVDS loopback the output of the LR is passed to the LD via "Rx
LVDS LoopBack Mux". Bit 0 of the header cannot be guaranteed to be asserted when the
incoming data from the other device is looped back. In this loopback, the Rx Interface
Controller operates in normal mode, decoding the frames (header, payloads) but the Tx
Interface Controller is ignored.

Figure 676. Rx LoopBack mode

S/W programs TMCR[LPON] = 1.
For Slave Only: - Reception of ICLC Frame with Payload FFh (Loopback mode
on), from LFAST Master
DocID027809 Rev 4
Rx CONTROLLER
Tx CONTROLLER
CSR
TX FIFO
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