Soft Reset Command Description - STMicroelectronics SPC572L series Reference Manual

RM0400
When the flush control is detected, all filter TAPs are cleared and the DEC_COUNTER[3:0]
field in the status register DECFILTER_MSR is reset.
The flush function does not clear the Coefficient registers file in the Decimation Filter, thus it
is not required to re-write these registers after a flush. The integrator accumulator and
sample count are not cleared either. The output buffer also keeps the last result and may be
retrieved until the next output is posted.
The flush control precedes the input data to be filtered. Therefore, the corresponding
sample data is processed by the block after the flush. When ISEL=1, the field FLUSH in the
DECFILTER_IB register is processed. Note that a word of valid sample data can be
available at the same time the flush signal is asserted. In this case the flush is executed and
the sample is processed after the flush.
When the filter is disabled by the FTYPE[1:0] control bit field, the flush command is not
executed.
37.4.9

Soft reset command description

The soft reset command is requested through the self-negated bit SRES of the
DECFILTER_MCR register and provides the CPU with the capability to initialize the
Decimation Filter through the slave-bus interface. The procedure below must be performed
for a software reset when the filter is active:
1. disable filter inputs, writing DECFIL_MCR bit IDIS = 1.
2. poll the register DECFIL_MSR until the bit BSY is 0.
3. repeat the step 2 polling; this is necessary to cover the case when a sample is left in
the input buffer.
4. write DECFILTER_MCR bit SRES = 1.
After the software reset is issued, all internal Filter TAP registers, the decimation counter,
the integrator outputs (except DECFILTER_CINTCNT) and the state machine are put in the
initial state. The status register DECFILTER_MSR is also cleared. The Coefficient registers
are not affected by the SRES. In case there is some filter processing, the filter process is
aborted and the last sample is discarded. In addition, data in the input buffer waiting to be
processed, and data in the output buffer waiting to be read, are discarded (the requests of
service are cleared). The software reset command has high priority and the BSY bit is set
during its operation.
The configuration registers DECFILTER_MXCR and DECFILTER_MCR are also not
affected by a soft reset, except the bit SRES that is self-negated and is always read as zero.
When in debug or freeze mode, the soft reset is executed but the filter remains in debug or
freeze mode.
Note: It is recommended to clear the IBIE bit before a software reset, especially if ISEL changes,
in order to avoid unwanted interrupt requests.
Note: DMA transfers must not be active during soft reset. Data loss can occur.
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Decimation Filter
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