STMicroelectronics SPC572L series Reference Manual page 803

RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter-
1. Program the PDEDR register with appropriate power down exit delay value.
2. Exit the power down mode by clearing the MCR[PWDN] bit. After the power down
mode is exited the SARADC enters the IDLE state, this can be checked by polling for
MSR[ADCSTATUS] bits. Note: steps 3-7 can also be executed before step 2.
3. Program the required conversion mode and control options for e.g. one-shot mode or
scan mode, hardware trigger enable and selection for normal or injected conversions,
hardware trigger edge select, owerwrite enable e.t.c. in MCR register.
4. Program the conversion mask registers({I,T}C{N,J}CMR) for channels to be converted.
If required, enable and select watchdog monitors({I,T}CWENR, {I,T}CWSELR) as
applicable for each channel, program the watchdog threshold values(WTHRHLR) for
each watchdog monitor.
5. If required, Enable and select the , Test to internal channel mapping by programming
the TCCAPR registers.
6. Program the required Interrupt/DMA mask registers(DMAE, {I,T}CDSR, IMR,
{I,T}C{N,J}MR, WTIMR) for each of the selected channels.
7. Program the Conversion timing registers(CTR0-3) for the required conversion
durations. Enable the Precharge phase, reference selection, CTR selection per
channel basis by programming the {I,T}CDR registers.
8. To initiate Normal/Injected mode conversions by software set the
MCR[NSTART/JSTART] bit. To initiate hardware triggered Normal/Injected conversions
program the external trigger module to provide the required triggers.
9. Read the conversion data and status in {I,T}CDR registers.
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