Table 1000. Jdc_Msr Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

JTAG Data Communication (JDC)
61.3.1.2 Module status register (JDC_MSR)
Figure 1047
status and interrupt bits. This register is reset by system destructive reset.
Address
0x04
:
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
The JDC_MSR is described in
Field
JIN Ready (read only).
JIN_RDY
0 Cleared upon software read of JDC_JIN_IPS contents via IPS
1 Set when new data is written to the JDC_JIN_IPS register
JIN Interrupt.
JIN_INT
0 Cleared by writing logic 1
1 Set when new data is written to the JDC_JIN_IPS register
JOUT Ready (read only).
JOUT_RDY
0 Cleared upon tool read of JOUT register via JTAG port
1 Set when new data is written to the JDC_JOUT_IPS register
JOUT Interrupt.
JOUT_INT
0 Cleared by writing logic 1
1 Set when JOUT_RDY bit is cleared by tool reading JOUT register
61.3.1.3 JTAG output IPS data register (JDC_JOUT_IPS)
The JDC_JOUT_IPS register holds data written via IPS. The JDC_JOUT_IPS contents are
ported out and captured into the JOUT register to be read via the JTAG port.
shows the format of the JDC_JOUT_IPS register. This register is reset by system
destructive reset.
1798/2058
shows the format of the JDC_MSR.The JDC_MSR holds the JTAG register
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 1047. Module Status Register (JDC_MSR)
Table

Table 1000. JDC_MSR register field descriptions

DocID027809 Rev 4
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
1000.
Description
Access: User w1c
10 11 12 13
0 0 0
0 0 0 0
26 27 28 29
0 0 0
0 0 0 0
Figure 1048
RM0400
14 15
0
w1c
0 0
30 31
0
w1c
0 0