STMicroelectronics SPC572L series Reference Manual page 688

Error Injection Module (EIM)
Table 335. Error Injection Channel Enable register (EICHEN) field description(Continued)
Name
27
EICH4EN
26
EICH5EN
33.2.2.3 Error Injection Channel n Descriptor (EICHDn)
Each 96-bit (12-byte) error injection channel descriptor specifies a mask that defines which
bits of the read data and checkbit bus from target RAM are inverted on a read access. The
error injection channel descriptors are organized sequentially as 128-bit (16-byte) structures
in the Error Injection Module programming model. Each of the three 32-bit words that define
a single error injection channel are detailed in the subsequent sections; the fourth word is
unused.
In the subsequent sections the terminology, upper word, is used to describe bits 63–32 of a
64-bit data bus.
In the subsequent sections the terminology, lower word, is used to describe bits 31–0 of a
64-bit data bus.
33.2.2.3.1 Error Injection Channel n Descriptor, Word0 (EICHDn.Word0)
The first word of the Error Injection Channel n Descriptor defines an 8-bit mask
(CHKBIT_MASK). Each bit of CHKBIT_MASK specifies if the corresponding bit of the
checkbit bus from the target RAM should be inverted or left unmodified on read accesses.
Successful writes to this word clear the corresponding error injection channel valid bit,
EICHEN[EICHnEN].
688/2058
Error Injection Channel 4 Enable.
This bit enables the corresponding error injection channel. There is a global error injection
enable (EIMCR[GEIEN]) also that must be asserted to enable error injection. Once error
injection is enabled, all subsequent read accesses will incur bit inversion(s) as defined in
Error Injection Descriptor4 registers (EICHD4) until the error injection channel is manually
disabled via software.
Any write to the corresponding EICHDn registers clears the corresponding
EICHEN[EICHnEN] bit, leaving the error injection channel disabled. This bit is cleared by
power-on reset and unaffected by other types of system reset.
0 Error injection is disabled on Error Injector Channel 4
1 Error injection is enabled on Error Injector Channel 4
Error Injection Channel 5 Enable.
This bit enables the corresponding error injection channel. There is a global error injection
enable (EIMCR[GEIEN]) also that must be asserted to enable error injection. Once error
injection is enabled, all subsequent read accesses will incur bit inversion(s) as defined in
Error Injection Descriptor5 registers (EICHD5) until the error injection channel is manually
disabled via software.
Any write to the corresponding EICHDn registers clears the corresponding
EICHEN[EICHnEN] bit, leaving the error injection channel disabled. This bit is cleared by
power-on reset and unaffected by other types of system reset.
0 Error injection is disabled on Error Injector Channel 5
1 Error injection is enabled on Error Injector Channel 5
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