Table 690. Recommended Receive Exception Handling Mechanism - STMicroelectronics SPC572L series Reference Manual

LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communications
47.7.8.3 Receive complete interrupt
This interrupt indicates a reception of a frame. This interrupt is asserted whenever any of
the following bits is set in the RISR along with the corresponding interrupt enable bit is also
set in the RIER.
•
RXCTSF
•
RXDF
•
RXUNSF
Each of these bits are individually maskable. So, the bits that are not required to generate
an interrupt to the processor can be masked by clearing its bit in the RIER. Once the
interrupt is asserted, it can be negated by clearing the corresponding flag bit in the RISR.
47.7.8.4 Receive exception interrupt
This interrupt indicates occurrence of an exception condition in Rx block. This interrupt is
asserted whenever any of the following bits is set in the RISR and corresponding enable
mask bit is also set in the RIER.
•
RXLCEF
•
RXICF
•
RXSZF
•
RXUOF
•
RXUFF
•
RXMXF
•
RXMNF
•
RXOFF
Each of these bits are individually maskable. So, those bits that are not required to generate
an interrupt to the processor can be masked by clearing the appropriate bit in the RIER. For
details on the cause of assertion of each bit refer to the RISR description. Once the interrupt
is asserted, it can be negated by clearing the corresponding flag bit in the RISR.
Exception
RXLCEF
RXICF
RXSZF
RXOFF
RXUFF
RXMXF
RXMNF
RXUNSF
1284/2058

Table 690. Recommended receive exception handling mechanism

The MCR[RXEN] may be set and cleared, as this exception can result in loss
of subsequent packet
No action required
The MCR[RXEN] may be set and cleared, as this exception can result in loss
of subsequent packet
– The MCR[RXEN] may be cleared
– The system level interfaces receive may be reset and enabled, as current
transfer may be corrupted
No action required
The system level interfaces receive should be enabled, if not enabled
No action required
No action required
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