Related Manuals for Altera SDI HSMC
Summary of Contents for Altera SDI HSMC
- Page 1 SDI HSMC Reference Manual 101 Innovation Drive Document Version: San Jose, CA 95134 Document Date: July 2009 www.altera.com...
- Page 2 Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation.
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Page 3: Table Of Contents
How to Contact Altera ........ - Page 4 SDI HSMC Reference Manual © July 2009 Altera Corporation...
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Page 5: Chapter 1. Overview
General Description This manual provides information about the hardware features of the serial digital interface (SDI) high-speed mezzanine card (HSMC). You can use the SDI HSMC to design and implement SDI and Audio Engineering Society (AES) systems based on transceiver-supported host boards with HSMC interfaces. Altera ®... -
Page 6: Development Board Block Diagram
GX FPGA development board, refer to the Stratix IV GX FPGA Development Board Reference Manual. Figure 1–1. SDI HSMC Connected to the Stratix IV GX FPGA Development Board Stratix IV GX FPGA Development Board SDI HSMC Development Board Block Diagram Figure 1–2... -
Page 7: Aes
Table 1–1. Frequency Setup of the VCXO PLL Frequency (MHz) S [2:0] Pin 5 Pin 6 98.304 98.304 90.3168 90.3168 122.88 122.88 112.896 112.896 98.304 122.88 90.3168 112.896 98.304 90.3168 122.88 112.896 © July 2009 Altera Corporation SDI HSMC Reference Manual... -
Page 8: Handling The Board
Static Discharge Precaution: Without proper anti-static handling, the board can be damaged. Therefore, use anti-static handling precautions when touching the board. The SDI HSMC must be stored between –40° C and 100° C. The recommended operating temperature is between 0° C and 55° C. -
Page 9: Introduction
■ “Restoring Board to Factory Defaults” on page 2–25 ■ Board Overview This section provides an overview of the SDI HSMC, including an annotated board image and component descriptions. Figure 2–1 shows the top-view of the SDI HSMC, including its components and interface locations. - Page 10 Buffer Video PLL (U6) (J62) (J18) (J17) Figure 2–2 shows the bottom view of the SDI HSMC. Figure 2–2. Bottom View of the SDI HSMC (HSMC Connector View) SDI Cable Equalizer (U8) RS422 Transceiver (U9) SDI Cable Equalizer (U10) HSMC...
- Page 11 Chapter 2: Board Components 2–3 Board Overview Table 2–1 describes the components and lists their corresponding board references. Table 2–1. SDI HSMC Components (Part 1 of 2) Board Reference Name Description Devices U1, U2 SDI cable tri-speed driver Input signal to this driver is from the HSMC high-speed serializer/deserializer (SERDES) section.
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Page 12: Supported Protocols
Components and Interfaces HSMC connector SDI HSMC’s main interface to the host board. The host must support 3-Gbps interfacing on transceiver channels 0 and 1 (first 2 channels) which are located at pins 25 – 32. The control, clock, and AES signals are located in the general CMOS signal area. -
Page 13: Configuration, Status, And Setup Elements
2–5 Configuration, Status, and Setup Elements Although there is only one clock generator PLL on the SDI HSMC, the board supports two asynchronous clock systems when the host board supports two reference clock input signals. You can use either a separate reference clock or an external reference as input to the host board. -
Page 14: Clock Circuitry
SMA outputs and also at the HSMC connector. The SMA outputs are provided for use as a low-jitter signal directed into a SERDES reference clock input on the host board. Figure 2–3 shows the SDI HSMC clocking diagram. SDI HSMC Reference Manual © July 2009 Altera Corporation... - Page 15 Chapter 2: Board Components 2–7 Clock Circuitry Figure 2–3. SDI HSMC Clocking Diagram VSYNC Video Sync HSYNC Separator Video In 27.000 MHz EXTCLK_OUT (P) EXTCLK_OUT (N) 26.973 MHz SDI CLK Differential Buffer SDI CLK (P) SDI HSMC CLK SDI CLK (N)
- Page 16 2–6). The output frequency can be 148.5 MHz, 74.25 MHz, 54 MHz, or 36 MHz. The output frequency is set to 148.5 MHz for the Altera reference design and most applications. Table 2–5 lists the first frequency translation stage of the SDI multi-frequency VCXO femto clock video PLL.
- Page 17 — — 1,10 27 MHz 54 MHz — — 1,11 27 MHz 36 MHz — — Table 2–7 shows the bypass function of the SDI multi-frequency VCXO femto clock video PLL. © July 2009 Altera Corporation SDI HSMC Reference Manual...
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Page 18: Host Board Reference Clock
100-MHz oscillator, you can divide the frequency by 6,400 to 15.625 kHz and drive that frequency to the clock generator to be multiplied to 148.5 MHz. Altera recommends locking the VCXO PLL to a stable oscillator which is located on the host board when the daughtercard is sourcing data or when the VCXO PLL is not locked onto a received signal or reference. -
Page 19: Loop Back Reference Clock From Sdi Input
HSMC interface to the clock generator on the SDI HSMC. The clock output from the host is cleaned (jitter), multiplied to 148.5 MHz, and driven back to the host board to be used as the SERDES reference clock. - Page 20 Crystal Input External Capacitors PDTS Table 2–9 shows the audio rate and clock frequencies supported by the SDI HSMC. Table 2–9. Audio Sample Rate versus Clock Frequency (Part 1 of 2) Audio Sample Rate (kHz) Bit Rate Clock (MHz) Oversampling Rate VCXO Frequency 24.00...
- Page 21 Table 2–10. VCXO PLL Frequency Output CLK1 (MHz) CLK2 (MHz) CLK3 CLK4 98.304 98.304 90.3168 90.3168 122.88 122.88 112.896 112.896 98.304 122.88 90.3168 112.896 98.304 90.3168 122.88 112.896 © July 2009 Altera Corporation SDI HSMC Reference Manual...
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Page 22: Audio/Video Input And Output
2–14 Chapter 2: Board Components Audio/Video Input and Output Audio/Video Input and Output This section describes the I/O channels of the SDI HSMC which includes: SDI RX Channels ■ SDI TX Channels ■ AES3 RX Channels ■ ■ AES3 TX Channels... -
Page 23: Sdi Tx Channels
LED. For the TX channel circuit diagram, refer to the schematic page entitled SDI Cable Driver on page 5 of Altera schematic 150-0320610-B1. In Altera development kits that contain the SDI HSMC, this schematic resides in the <install dir>\board_design_files directory. - Page 24 Figure 2–8 shows the SDI TX channel block diagram. Figure 2–8. SDI TX Channel Block Diagram DC Block Diff Term SDI Cable Rate Tri-speed Driver Network + Term DC Block SDI TX SDI HSMC Reference Manual © July 2009 Altera Corporation...
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Page 25: Aes3 Rx Channels
75 Ω and a return loss of 25 dB or more. The peak-to-peak output voltage is 1.0 V centered around the ground of the transmitter. Figure 2–10 shows the AES3 TX channel block diagram. © July 2009 Altera Corporation SDI HSMC Reference Manual... -
Page 26: General User Input/Output
(J5 and J7). When jumpers are not installed on J5 and J7, the EQ_BYPASS signal can be controlled from the host device. Table 2–11 lists the jumper descriptions and schematic signal names. SDI HSMC Reference Manual © July 2009 Altera Corporation... -
Page 27: Components And Interfaces
Components and Interfaces This section describes the SDI HSMC interface. The SDI HSMC contains an Altera standard HSMC connector to connect to a host board. All the other connector interfaces on the SDI HSMC are connected to the HSMC connector. - Page 28 2–20 Chapter 2: Board Components Components and Interfaces Figure 2–11. HSMC Connector Bank 1 Pin-Outs SDI_EQOUT_P2 SDI_TX_P2 SDI_EQOUT_N2 SDI_TX_N2 SDI_EQOUT_P1 SDI_TX_P1 SDI_EQOUT_N1 SDI_TX_N1 JTAG_TDO_TDI JTAG_TDO_TDI SDI HSMC Reference Manual © July 2009 Altera Corporation...
- Page 29 3.3 V SDI_RATE_SEL1 SDI_RATE_SEL2 12 V 3.3 V EQ_BYPASS1 EQ_BYPASS2 12 V 3.3 V AES_CLK_S0 AES_CLK_S1 3.3 V 12 V AES_CLK_S2 AES_CLK_PDTSn 12 V 3.3 V AES_CLK 12 V 3.3 V © July 2009 Altera Corporation SDI HSMC Reference Manual...
- Page 30 12 V SDI_CLK_V1 SDI_CLK_V2 3.3 V 12 V ODDEVEN SDI_CLK_V3 VFORMAT SDI_CLK_MLTF 12 V 3.3 V VSYNC SDI_CLK_RST HSYNC SDI_CLK_OE 12 V 3.3 V SDI_HSMC_CLK_P SDI_HSMC_CLK SDI_HSMC_CLK_N 3.3 V HSM_PSNTn R104 SDI HSMC Reference Manual © July 2009 Altera Corporation...
- Page 31 SDI_XTAL_SEL SDI clock control Input CMOS SDI_CLK_BP0 SDI clock control Input CMOS SDI_CLK_BP1 SDI clock control Input CMOS SDI_CLK_N0 SDI clock control Input CMOS SDI_CLK_N1 SDI clock control Input CMOS SDI_CLK_V0 © July 2009 Altera Corporation SDI HSMC Reference Manual...
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Page 32: Power Supply
Samtec ASP-122952-01 www.samtec.com Power Supply The host board provides 12-V DC and 3.3-V DC power to the SDI HSMC through the HSMC connector. These power supplies are either used directly or regulated by an on-board regulator as required. Figure 2–14 shows the power distribution system of the SDI HSMC. -
Page 33: Restoring Board To Factory Defaults
PLL 3.3 V (LT3080) Power Plane 0.x A Restoring Board to Factory Defaults To restore the SDI HSMC to the factory default settings, perform the following steps: Install jumpers J4 and J6 (CD_MUTE) ■ ■ Remove all other jumpers © July 2009 Altera Corporation... - Page 34 2–26 Chapter 2: Board Components Restoring Board to Factory Defaults SDI HSMC Reference Manual © July 2009 Altera Corporation...
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Page 35: Additional Information
Email custrain@altera.com Product literature Website www.altera.com/literature Non-technical support (General) Email nacomp@altera.com (Software Licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. © July 2009 Altera Corporation SDI HSMC Reference Manual... -
Page 36: Typographic Conventions
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