Receive Fifo Overflow - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
In case 2: decoded watermark level of
time of the burst request is made is equal to the DMA burst length. Thus, the transmit FIFO may be full,
but not overflowed, at the completion of the burst transaction. †
Therefore, for optimal operation, DMA burst length must be set at the FIFO level that triggers a transmit
DMA request; that is: †
DMA burst length =
Adhering to this equation reduces the number of DMA bursts needed for block transfer, and this in turn
improves bus utilization. †
The transmit FIFO will not be full at the end of a DMA burst transfer if the UART controller has success‐
fully transmitted one data item or more on the UART serial transmit line during the transfer. †

Receive FIFO Overflow

During UART serial transfers, receive FIFO requests are made to the DMA whenever the number of
entries in the receive FIFO is at or above the decoded level of Receive Trigger (
Control Register (
of data from the receive FIFO. †
Data should be fetched by the DMA often enough for the receive FIFO to accept serial transfers continu‐
ously, that is, when the FIFO begins to fill, another DMA transfer is requested. Otherwise the FIFO will fill
with data (overflow)​. To prevent this condition, the user must set the watermark level correctly. †
Receive Watermark Level
Similar to choosing the transmit watermark level described earlier, the receive watermark level, decoded
watermark level of
Receive FIFO Buffer diagram. It is a tradeoff between the number of DMA burst transactions required per
block versus the probability of an overflow occurring. †
Receive FIFO Underflow
Setting the source transaction burst length greater than the watermark level can cause underflow where
there is not enough data to service the source burst request. Therefore, the following equation must be
adhered to avoid underflow: †
DMA burst length = decoded watermark level of
If the number of data items in the receive FIFO is equal to the source burst length at the time of the burst
request is made, the receive FIFO may be emptied, but not underflowed, at the completion of the burst
transaction. For optimal operation, DMA burst length should be set at the watermark level, decoded
watermark level of
Adhering to this equation reduces the number of DMA bursts in a block transfer, which in turn can avoid
underflow and improve bus utilization. †
The receive FIFO will not be empty at the end of the source burst transaction if the UART controller has
successfully received one data item or more on the UART serial receive line during the burst. †
UART Controller
Send Feedback
IIR_FCR.TET
- decoded watermark level of
FIFO_DEPTH
). This is known as the watermark level. The DMA responds by fetching a burst
IIR_FCR
, should be set to minimize the probability of overflow, as shown in the
IIR_FCR.RT
. †
IIR_FCR.RT
= 64, the amount of space in the transmit FIFO at the
IIR_FCR.TET
+ 1
IIR_FCR.RT
Receive FIFO Overflow
) field in the FIFO
RT
Altera Corporation
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