Document Revision History - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Module Instance
spis0
spis1
Offset:
0x60 to 0xEC
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
dr Fields
Bit
15:0
dr

Document Revision History

Table 19-7: Document Revision History
Date
October 2016
May 2016
SPI Controller
Send Feedback
0xFFE02000
0xFFE03000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
When writing to this register, you must right-justify
the data. Read data are automatically right-justified.
Read = Receive FIFO buffer Write = Transmit FIFO
buffer
Version
2016.10.28 Maintenance release.
2016.05.03 Maintenance release.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
dr
RW 0x0
Description
Document Revision History
Register Address
0xFFE02060 to
0xFFE020EC
0xFFE03060 to
0xFFE030EC
21 20 19 18
5 4 3 2
Access
Changes
19-85
17 16
1 0
Reset
RW 0x0
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