Uart(Rs232) Serial Protocol - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

UART(RS232) Serial Protocol

Because the serial communication between the UART controller and the selected device is asynchronous,
additional bits (start and stop) are added to the serial data to indicate the beginning and end. Utilizing
these bits allows two devices to be synchronized. This structure of serial data accompanied by start and
stop bits is referred to as a character, as shown in below.†
Figure 21-2: Serial Data Format
Serial Data
An additional parity bit may be added to the serial character. This bit appears after the last data bit and
before the stop bit(s) in the character structure to provide the UART controller with the ability to perform
simple error checking on the received data.†
The Control Register is used to control the serial character characteristics. The individual bits of the data
word are sent after the start bit, starting with the least- significant bit (LSB). These are followed by the
optional parity bit, followed by the stop bit(s), which can be 1, 1.5 or 2.†
All the bits in the transmission (with exception to the half stop bit when 1.5 stop bits are used) are
transmitted for exactly the same time duration. This is referred to as a Bit Period or Bit Time. One Bit
Time equals 16 baud clocks. To ensure stability on the line, the receiver samples the serial input data at
approximately the midpoint of the Bit Time once the start bit has been detected. Because the exact number
of baud clocks that each bit transmission is known, calculating the midpoint for sampling is not difficult.
That is, every 16 baud clocks after the midpoint sample of the start bit.†
Together with serial input debouncing, this feature also contributes to avoid the detection of false start
bits. Short glitches are filtered out by debouncing, and no transition is detected on the line. If a glitch is
wide enough to avoid filtering by debouncing, a falling edge is detected. However, a start bit is detected
only if the line is sampled low again after half a bit time has elapsed. †
Figure 21-3: Receiver Serial Data Sample Points
Serial Data In
The baud rate of the UART controller is controlled by the serial clock and the Divisor Latch Register
( DLH and DLL ).†
Automatic Flow Control
The UART includes 16750-compatible request-to-send (RTS) and clear-to-send (CTS) serial data
automatic flow control mode. You enable automatic flow control with the modem control register
(
MCR.AFCE
UART Controller
Send Feedback
Bit Time
Data Bits 5 - 8
Start
Start
8
). †
Parity
One Character
Data Bit 0 (LSB)
16
UART(RS232) Serial Protocol
1, 1.5, 2
Stop Bits
Data Bit 1
16
Altera Corporation
21-5