Functional Description Of The Uart Controller - Altera cyclone V Technical Reference

21-4

Functional Description of the UART Controller

Signal
uart_cts
uart_rts
uart_dsr
uart_dcd
uart_ri
uart_dtr
uart_out1_n
uart_out2_n
Functional Description of the UART Controller
The HPS UART is based on an industry-standard 16550 UART. The UART supports serial communication
with a peripheral, modem (data carrier equipment), or data set. The master (CPU) writes data over the
slave bus to the UART. The UART converts the data to serial format and transmits to the destination
device. The UART also receives serial data and stores it for the master (CPU). †
The UART's registers control the character length, baud rate, parity generation and checking, and
interrupt generation. The UART's single interrupt output signal is supported by several prioritized
interrupt types that trigger assertion. You can separately enable or disable each of the interrupt types with
the control registers. †
FIFO Buffer Support
The UART controller includes 128-byte FIFO buffers to buffer transmit and receive data. FIFO buffer
access mode allows the master to write the receive FIFO buffer and to read the transmit FIFO buffer for
test purposes. FIFO buffer access mode is enabled with the FIFO access register (
control portions of the transmit and receive FIFO buffers are reset and the FIFO buffers are treated as
empty. †
When FIFO buffer access mode is enabled, you can write data to the transmit FIFO buffer as normal;
however, no serial transmission occurs in this mode and no data leaves the FIFO buffer. You can read back
the data that is written to the transmit FIFO buffer with the transmit FIFO read (
register provides the current data at the top of the transmit FIFO buffer. †
Similarly, you can also read data from the receive FIFO buffer in FIFO buffer access mode. Since the
normal operation of the UART is halted in this mode, you must write data to the receive FIFO buffer to
read it back. The receive FIFO write (
bits of the 10-bit register write framing errors and parity error detection information to the receive FIFO
buffer. Bit 9 of
read these bits back from the receive buffer register, you can check the bits by reading the line status
register (
LSR
FIFO buffer. †
Altera Corporation
Width
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
indicates a framing error and bit 8 of
RFW
), and by checking the corresponding bits when the data in question is at the top of the receive
Direction
Input
Output
Input
Input
Input
Output
Output
Output
) register writes data to the receive FIFO buffer. The upper two
RFW
indicates a parity error. Although you cannot
RFW
Description
Clear to send
Request to send
Data set ready
Data carrier detect
Ring indicator
Data terminal ready
User defined output 1
User defined output 2
). Once enabled, the
FAR
) register. The
TFR
UART Controller
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cv_5v4
2016.10.28
TFR