Transmit Fifo Underflow - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Transmit FIFO Underflow

During UART serial transfers, transmit FIFO requests are made to the DMA controller whenever the
number of entries in the transmit FIFO is less than or equal to the decoded level of the Transmit Empty
Trigger (
TET
controller responds by writing a burst of data to the transmit FIFO buffer, of length specified as DMA
burst length. †
Data should be fetched from the DMA often enough for the transmit FIFO to perform serial transfers
continuously, that is, when the FIFO begins to empty, another DMA request should be triggered.
Otherwise, the FIFO will run out of data (underflow)​ causing a STOP to be inserted on the UART bus. To
prevent this condition, you must set the watermark level correctly. †
Related Information
DMA Controller
For more information, refer to the DMA Controller chapter.
Transmit Watermark Level
Consider the example where the following assumption is made: †
DMA burst length =
Here the number of data items to be transferred in a DMA burst is equal to the empty space in the
transmit FIFO. Consider the following two different watermark level settings: †
IIR_FCR.TET = 1
IIR_FCR.TET
• Transmit FIFO watermark level = decoded watermark level of
• DMA burst length =
• UART transmit
• Block transaction size = 448†
Figure 21-8: Transmit FIFO Watermark Level = 16
Transmit FIFO
Watermark Level
Data Out
The number of burst transactions needed equals the block size divided by the number of data items per
burst:
Block transaction size/DMA burst length = 448/112 = 4
UART Controller
Send Feedback
) field in the FIFO Control Register (
on page 16-1
- decoded watermark level of
FIFO_DEPTH
= 1 decodes to a watermark level of 16.
- decoded watermark level of
FIFO_DEPTH
= 128 †
FIFO_DEPTH
FIFO_DEPTH = 128
), also known as the watermark level. The DMA
FCR
Transmit
FIFO Buffer
FIFO_DEPTH - IIR_FCR.TET = 112
Empty
Decoded watermark
Full
level of IIR_FCR.TET = 16
Transmit FIFO Underflow
†
IIR_FCR.TET
= 16 †
IIR_FCR.TET
= 112 †
IIR_FCR.TET
Data In
21-11
DMA
Controller
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