Master Mode Operation - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Master Mode Operation

Initial Configuration
For master mode operation, the target address and address format can be changed dynamically without
having to disable the I
master because the slave requires the component to be disabled before any changes can be made to the
address. To use the I
For multiple I
become empty during the I
master stalls the transfer by holding the SCL line low because there was no stop bit indicating the master
to issue a STOP. The master will complete the transfer when it finds a Tx FIFO entry tagged with a Stop
bit.
1. Disable the I
2. Write to the
and to specify whether the I
device is a slave (bit 3). †
3. Write to the
General Call or a START BYTE command is going to be performed by I
2
I C controller master-initiated transfers, either 7-bit or 10-bit addressing, is controlled by the
IC_10BITADDR_MASTER
4. Enable the I
5. Now write the transfer direction and data to be sent to the
register is written before the I
kept cleared when the I
Dynamic IC_TAR or IC_10BITADDR_MASTER Update
2
The I C controller supports dynamic updating of the
bit fields of the
conditions are met: †
2
• The I C controller is not enabled (
2
• The I C controller is enabled (
RX) operation (
(
IC_CON[0]
Master Transmit and Master Receive
2
The I C controller supports switching back and forth between reading and writing dynamically. To
transmit data, write the data to be written to the lower byte of the I
Register (
IC_DATA_CMD
read command may be issued by writing "don't cares" to the lower byte of the
1 should be written to the CMD bit.†
I2C Controller
Send Feedback
2
C controller. This feature is only applicable when the I
2
C controller as a master, perform the following steps: †
2
C transfers, perform additional writes to the Tx FIFO such that the Tx FIFO does not
2
C transaction. IF the Tx FIFO is completely emptied at any stage, then the
2
C controller by writing 0 to bit 0 of the
register to set the maximum speed mode supported for slave operation (bits 2:1)
IC_CON
2
C controller starts its transfers in 7/10 bit addressing mode when the
register the address of the I
IC_TAR
bit field (bit 12). †
2
C controller by writing a 1 in bit 0 of the
2
C controller is enabled, the data and commands are lost as the buffers are
2
C controller is not enabled. †
register. You can dynamically write to the
IC_TAR
IC_ENABLE
IC_ENABLE
=0); AND I
IC_STATUS[5]
=1); AND there are no entries in the TX FIFO (
). The CMD bit [8] should be written to 0 for I
register. †
IC_ENABLE
2
C device to be addressed. It also indicates whether a
register. †
IC_ENABLE
IC_DATA_CMD
(bits 9:0) and
IC_TAR
IC_TAR
=0); †
2
=1); AND I C controller is NOT engaged in any Master (TX,
2
C controller is enabled to operate in Master mode
IC_STATUS[2]
2
C Rx/Tx Data Buffer and Command
Master Mode Operation
2
C controller is acting as a
2
C. The desired speed of the
register. If the
IC_DATA_CMD
IC_10BITADDR_MASTER
register provided the following
=1) †
2
C write operations. Subsequently, a
register, and a
IC_DATA_CMD
Altera Corporation
20-19
(bit 12)