Resets - Altera cyclone V Technical Reference

28-6

Resets

emac_ptp_ref_clock
qspi_sclk_out
spim_sclk_out
spis_sclk_in
i2c_clk
i2c_scl_in
Resets
This section describes the reset interfaces to the HPS component.
Related Information
Reset Manager
For details about the HPS reset sequences, refer to the Functional Description of the Reset Manager in the
Reset Manager chapter .
HPS-to-FPGA Reset Interfaces
The following interfaces allow the HPS to reset soft logic in the FPGA fabric:
•
h2f_reset
•
h2f_cold_reset
•
h2f_warm_reset_handshake
FPGA
HPS External Reset Request
The following interfaces allow soft logic in the FPGA fabric to request for different types of HPS resets:
•
f2h_cold_reset_req
•
f2h_warm_reset_req
•
f2h_dbg_reset_req
Altera Corporation
Clock Name
on page 3-1
—HPS-to-FPGA warm reset
—HPS-to-FPGA cold reset
—Warm reset request and acknowledge interface between HPS and
—FPGA-to-HPS cold reset request
—FPGA-to-HPS warm reset request
—FPGA-to-HPS debug reset request
Description
Ethernet timestamp precision time protocol (PTP)
reference clock
QSPI master clock output
SPI master serial clock output
SPI slave serial clock input
2
I C outgoing clock (part of the SCL bidirectional
pin signals)
2
I C incoming clock (part of the SCL bidirectional
pin signals)
cv_5v4
2016.10.28
HPS Component Interfaces
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