I2C Module Address Map - Altera cyclone V Technical Reference

20-24 2
I C Controller Address Map and Register Definitions
2
I C Controller Address Map and Register Definitions
The address map and register definitions for the HPS-FPGA bridges consist of the following regions:
2
• I C Module 0
2
• I C Module 1
2
• I C Module 2
2
• I C Module 3
Related Information
Introduction to the Hard Processor System
•
For more information, refer to Introduction to the Hard Processor System chapter.
http://www.altera.com/literature/hb/cyclone-v/hps.html
•

I2C Module Address Map

Registers in the I2C module
i2c0
i2c1
i2c2
i2c3
I2C Module
Register
ic_con on page 20-26
ic_tar on page 20-29
ic_sar on page 20-31
ic_data_cmd
20-32
ic_ss_scl_hcnt
page 20-34
ic_ss_scl_lcnt
page 20-35
ic_fs_scl_hcnt
page 20-36
ic_fs_scl_lcnt
page 20-37
Altera Corporation
Module Instance
Offset
0x0
0x4
0x8
on page 0x10
on 0x14
on 0x18
on 0x1C
on 0x20
on page 1-1
0xFFC04000
0xFFC05000
0xFFC06000
0xFFC07000
Width Acces Reset Value
s
32 RW 0x7D
32 RW 0x1055
32 RW 0x55
32 RW 0x0
32 RW 0x190
32 RW 0x1D6
32 RW 0x3C
32 RW 0x82
Base Address
Description
Control Register
Target Address Register
Slave Address Register
Tx Rx Data and Command
Register
Std Spd Clock SCL HCNT
Register
Std Spd Clock SCL LCNT Register
Fast Spd Clock SCL HCNT
Register
Fast Spd Clock SCL LCNT
Register
Send Feedback
cv_5v4
2016.10.28
I2C Controller