Clocks - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Clocks

Table 23-1: Timer Clock Characteristics
Timer
OSC1 timer 0
OSC1 timer 1
SP timer 0
SP timer 1
The timers above are labeled according to the clock it receives. OSC timers receive the oscillator clock
osc1_clk
SP timer 0 and SP timer 1 must be disabled before
then re-enable the timer once the clock frequency change takes effect. You cannot change the frequency of
OSC1 timer 0 and OSC1 timer 1.
Related Information
Clock Manager
For more information about clock performance, refer to the Clock Manager chapter.
Resets
The timers are reset by a cold or warm reset. Resetting the timers produces the following results in the
following order:
1. The timer is disabled.
2. The interrupt is enabled.
3. The timer enters free-running mode.
4. The timer count load register value is set to zero.
Interrupts
The timer1 interrupt status (
the interrupts. The
timer1eoi
The timer1 control register (
(
timer1_interrupt_mask
of operation, the timer generates an interrupt signal when the timer count reaches zero and the interrupt
mask bit of the control register is high.
If the timer interrupt is set, then it is cleared when the timer is disabled.
FPGA Interface
The timer interrupts can be routed to the FPGA interface. You can configure and route the interrupts
when you instantiate the HPS component in Qsys.
Timer
Send Feedback
osc1_clk
l4_sp_clk
and the SP timers receives the l4 slave peripheral clock
on page 2-1
timer1intstat
register allows you to read the status of the interrupt. Reading from the
timer1intstat
register clears the interrupt. †
timer1controlreg
) to mask the interrupt. In both the free-running and user-defined count modes
System Clock
Timer must be disabled if clock
frequency changes
l4_sp_clk
is changed to another frequency. You can
l4_sp_clk
) and timer1 end of interrupt (
) contains the timer1 interrupt mask bit
Clocks
Notes
—
.
) registers handle
timer1eoi
Altera Corporation
23-3