Dma Controller Operation - Altera cyclone V Technical Reference

19-30

DMA Controller Operation

DMA Controller Operation
To enable the DMA controller interface on the SPI controller, you must write the DMA Control Register
( ). Writing a 1 to the TDMAE bit field of
DMACR
handshaking interface. Writing a 1 to the RDMAE bit field of the
receive handshaking.†
Related Information
DMA Controller
For details about the DMA controller, refer to the DMA Controller chapter.
Transmit FIFO Buffer Underflow
During SPI serial transfers, transmit FIFO buffer requests are made to the DMA Controller whenever the
number of entries in the transmit FIFO buffer is less or equal to the value in DMA Transmit Data Level
Register (
DMATDLR
of data to the transmit FIFO buffer, of length specified as DMA burst length.†
Note: Data should be fetched from the DMA often enough for the transmit FIFO buffer to perform serial
transfers continuously, that is, when the FIFO buffer begins to empty, another DMA request should
be triggered. Otherwise, the FIFO buffer will run out of data (underflow)​. To prevent this condition,
you must set the watermark level correctly.†
Related Information
DMA Controller
For details about the DMA burst length microcode setup, refer to the DMA Controller chapter.
Transmit FIFO Watermark
Therefore, the goal in choosing a watermark level is to minimize the number of transactions per block,
while at the same time keeping the probability of an underflow condition to an acceptable level. In
practice, this is a function of the ratio of the rate at which the SPI transmits data to the rate at which the
DMA can respond to destination burst requests. †
Example 1: Transmit FIFO Watermark Level = 64
Consider the example where the assumption is made: †
DMA burst length =
Here the number of data items to be transferred in a DMA burst is equal to the empty space in the
transmit FIFO buffer.
Consider the following:
• Transmit FIFO watermark level =
• DMA burst length =
• SPI transmit
• Block transaction size = 960 †
Altera Corporation
on page 16-1
); also known as the watermark level. The DMA Controller responds by writing a burst
on page 16-1
-
FIFO_DEPTH DMATDLR
DMATDLR
-
FIFO_DEPTH DMATDLR
= 256 †
FIFO_DEPTH
register enables the SPI controller transmit
DMACR
DMACR
= 64 †
= 192 †
register enables the SPI controller
SPI Controller
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2016.10.28