Slave Mode Operation - Altera cyclone V Technical Reference

20-16
Taking the I
2
Taking the I C Controller Out of Reset
When a cold or warm reset is issued in the HPS, the reset manager resets this module and holds it in reset
until software releases it.
After the Cortex-A9 MPCore CPU boots, it can deassert the reset signal by clearing the appropriate bits in
the reset manager's corresponding reset register. For details about reset registers, refer to "Module Reset
Signals".
Related Information
Modules Requiring Software Deassert
2
I C Controller Programming Model
This section describes the programming model for the I
operation modes. †
Note: Each I
simultaneously. Ensure that bit 6 (
register are never set to 0 and 1, respectively. †

Slave Mode Operation

Initial Configuration
To use the I
1. Disable the I
2. Write to the
controller responds. †
Note: The reset value for the I
address, you can safely skip this step.
3. Write to the
3). Enable the I
to bit 0 (
Note: Slaves and masters do not have to be programmed with the same type of addressing 7- or 10-bit
address. For instance, a slave can be programmed with 7-bit addressing and a master with 10-bit
addressing, and vice versa. †
4. Enable the I
Slave-Transmitter Operation for a Single Byte
When another I
controller acts as a slave-transmitter and the following steps occur: †
1. The other I
the
IC_SAR
2
2. The I
C controller acknowledges the sent address and recognizes the direction of the transfer to
indicate that it is acting as a slave-transmitter. †
2
3. The I
C controller asserts the
software to respond. †
Altera Corporation
2
C Controller Out of Reset
2
C controller should be set to operate only as an I
2
C controller as a slave, perform the following steps: †
2
C controller by writing a 0 to bit 0 of the
register (bits 9:0) to set the slave address. This is the address to which the I
IC_SAR
2
C controller slave address is 0x55. If you are using 0x55 as the slave
register to specify which type of addressing is supported (7- or 10-bit by setting bit
IC_CON
2
C controller in slave-only mode by writing a 0 into bit 6 (
). †
MASTER_MODE
2
C controller by writing a 1 in bit 0 of the
2
C master device on the bus addresses the I
2
C master device initiates an I
2
register of the I C controller †
RD_REQ
on page 3-9
2
C controllers based on the two master and slave
2
C master or as an I
) and 0 (
IC_SLAVE_DISABLE
IC_ENABLE
IC_ENABLE
2
C controller and requests data, the I
2
C transfer with an address that matches the slave address in
interrupt (bit 5 of the
IC_RAW_INTR_STAT
2
C slave, never set both
) of the
IC_MASTER_MODE
register. †
IC_SLAVE_DISABLE
register. †
register) and waits for
Send Feedback
cv_5v4
2016.10.28
IC_CON
2
C
) and a 0
2
C
I2C Controller