Gpio Interface Block Diagram And System Integration - Altera cyclone V Technical Reference

22-2

GPIO Interface Block Diagram and System Integration

GPIO Interface Block Diagram and System Integration
The figure below shows a block diagram of the GPIO interface. The following table shows a pin table of the
GPIO interface:
Figure 22-1: Cyclone V SoC GPIO
Table 22-1: GPIO Interface pin table
Pin Name
GPIO [28:0]
GPIO [57:29]
GPIO [66:58]
HLGPI [13:0]
Table 22-2: GPIO Interface pin table
Pin Name
HPS_DEDICATED_Q1
[12:1]
HPS_DEDICATED_Q2
[12:1]
HPS_DEDICATED_Q3
[12:1]
HPS_DEDICATED_Q4
[12:1]
Altera Corporation
gpio_rst_n[n]
Reset
Manager
clk
Clock
Manager
GPIO[28:0]
I/O
GPIO[57:29]
GPIO[66:58]
HLGPI[13:0]
GPIO 0 [28:0]
GPIO 1 [28:0]
GPIO 2 [8:0]
GPIO 2 [26:13]
Mapped to GPIO Signal Name
GPIO 0 [11:0]
GPIO 0 [23:12]
GPIO 1 [11:0]
GPIO 1 [23:12]
GPIO Interface
Interrupt &
Control
Register
Block
GPIO 0
GPIO 1
GPIO 2
Slave
Interface
L4 Peripheral Bus
Mapped to GPIO Signal
Name
Input / Output
Input / Output
Input / Output
Input / Output
Cortex A9 Subsystem
gpio_intr_in
Core Generic Interrupt
Controller
Comments
Input / Output
Input / Output
Input / Output
Input only
Comments
General-Purpose I/O Interface
cv_5v4
2016.10.28
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