Gpio Interface Programming Model - Altera cyclone V Technical Reference

22-4

GPIO Interface Programming Model

After the Cortex-A9 MPCore CPU boots, it can deassert the reset signal by clearing the appropriate bits in
the reset manager's corresponding reset register. For details about reset registers, refer to "Module Reset
Signals".
GPIO Interface Programming Model
Debounce capability for each of the input signals can be enabled or disabled under software control by
setting the corresponding bits in the
stable and operational before the debounce capability is enabled.
Under software control, the direction of the external I/O pad is controlled by a write to the
gpio_swportx_ddr
values on the signal of the external I/O pad. When configured as output mode, the data written to the
gpio_swporta_dr
and output modes, so they cannot be configured as input and output modes at the same time. †
General-Purpose I/O Interface Address Map and Register Definitions
The address map and register definitions for the GPIO consist of the following regions:
• GPIO Module 0
• GPIO Module 1
• GPIO Module 2
Related Information
Introduction to the Hard Processor System
•
For more information, refer to Introduction to the Hard Processor System chapter.
http://www.altera.com/literature/hb/cyclone-v/hps.html
•
GPIO Module Address Map
Registers in the GPIO module
gpio0
gpio1
gpio2
GPIO Module
Register
gpio_swporta_dr
page 22-5
gpio_swporta_ddr
page 22-6
Altera Corporation
register. When configured as input mode, reading
register drives the output buffer of the I/O pad. The same pins are shared for both input
Module Instance
Offset Width Acces
on 0x0
on 0x4
register, accordingly. The debounce clock must be
gpio_debounce
on page 1-1
0xFF708000
0xFF709000
0xFF70A000
Reset Value
s
32 RW 0x0
32 RW 0x0
would read the
gpio_ext_porta
Base Address
Description
Port A Data Register
Port A Data Direction Register
General-Purpose I/O Interface
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cv_5v4
2016.10.28