Uart Controller Signal Description - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Serial receiver
DMA interface
Related Information
DMA Controller
For more information, refer to the DMA Controller chapter.

UART Controller Signal Description

HPS I/O Pins
Table 21-2: HPS I/O UART Pin Descriptions
Pin
RX
TX
CTS
RTS
FPGA Routing
Table 21-3: Signals for FPGA Routing
Signal
uart_rxd
uart_txd
UART Controller
Send Feedback
Block
on page 16-1
Width
1 bit
1 bit
1 bit
1 bit
Width
1 bit
1 bit
UART Controller Signal Description
Converts the serial data character (as specified by
the control register) received in the UART format to
parallel form. Parity error detection, framing error
detection and line break detection is carried out in
this block. †
The UART controller includes a DMA controller
interface to indicate when received data is available
or when the transmit FIFO buffer requires data. The
DMA requires two channels, one for transmit and
one for receive. The UART controller supports
single and burst transfers. You can use DMA in
FIFO buffer and non-FIFO buffer mode.
Direction
Input
Output
Input
Output
Direction
Input
Output
Description
Description
Serial Input
Serial Output
Clear to send
Request to send
Description
Serial input
Serial output
Altera Corporation
21-3