Uart Controller Features - Altera cyclone V Technical Reference

Hard processor system
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2016.10.28
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The hard processor system (HPS) provides two UART controllers for asynchronous serial communication.
The UART controllers are based on an industry standard 16550 UART controller. The UART controllers
are instances of the Synopsys
(DW_apb_uart) peripheral.

UART Controller Features

The UART controller provides the following functionality and features:
• Programmable character properties, such as number of data bits per character, optional parity bits, and
number of stop bits †
• Line break generation and detection †
• Direct memory access (DMA) controller interface
• Prioritized interrupt identification †
• Programmable baud rate
• False start bit detection †
• Automatic flow control mode per 16750 standard †
• Internal loopback mode support
• 128-byte transmit and receive FIFO buffers
• FIFO buffer status registers †
• FIFO buffer access mode (for FIFO buffer testing) enables write of receive FIFO buffer by master
and read of transmit FIFO buffer by master †
• Shadow registers reduce software overhead and provide programmable reset †
• Transmitter holding register empty (THRE) interrupt mode †
Portions
2016 Synopsys, Inc. Used with permission. All rights reserved. Synopsys & DesignWare are
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©
registered trademarks of Synopsys, Inc. All documentation is provided "as is" and without any warranty.
Synopsys expressly disclaims any and all warranties, express, implied, or otherwise, including the implied
warranties of merchantability, fitness for a particular purpose, and non-infringement, and any warranties
arising out of a course of dealing or usage of trade.
†Paragraphs marked with the dagger (†) symbol are Synopsys Proprietary. Used with permission.
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos
©
are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
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APB Universal Asynchronous Receiver/Transmitter
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