Functional Description Of The Gpio Interface - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Related Information
http://www.altera.com/literature/hb/cyclone-v/cv_52005.pdf
For more information on I/O banks locations on device, refer to Cyclone V I/O Features.

Functional Description of the GPIO Interface

Debounce Operation
The GPIO modules provided in the HPS include optional debounce capabilities. The external signal can be
debounced to remove any spurious glitches that are less than one period of the external debouncing clock,
gpio_db_clk
When input signals are debounced using the
a minimum of two cycles of the debounce clock to guarantee that they are registered. Any input pulse
widths less than a debounce clock period are filtered out. If the input signal pulse width is between one
and two debounce clock widths, it may or may not be filtered out, depending on its phase relationship to
the debounce clock. If the input pulse spans two rising edges of the debounce clock, it is registered. If it
spans only one rising edge, it is not registered. †
The figure below shows a timing diagram of the debounce circuitry for both cases: a bounced input signal,
and later, a propagated input signal.
Figure 22-2: Debounce Timing With Asychronous Reset Flip-Flops
gpio_db_clk
gpio_ext_porta
gpio_intr_in
Note: Enabling the debounce circuitry increases interrupt latency by two clock cycles of the debounce
clock.
Pin Directions
The pins
GPIO0
through
HLGPI13
Taking the GPIO Interface Out of Reset
When a cold or warm reset is issued in the HPS, the reset manager resets this module and holds it in reset
until software releases it.
General-Purpose I/O Interface
Send Feedback
. †
The signal is not registered
because it does not meet the
debounce clock's 2-cycle
requirement.
through can be configured to be either input or output signals. The pins
GPIO66
share pins with the HPS DDR controller and are input-only signals.
Functional Description of the GPIO Interface
debounce clock, the signals must be active for
gpio_db_clk
This signal is registered because
it meets the debounce clock's 2-cycle
requirements
Because the signal is
registered, it generates
the interrupt signal.
Interrupt
Cleared
HLGPI0
Altera Corporation
22-3