Introduction To The Hps Component - Altera cyclone V Technical Reference

2016.10.28
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The hard processor system (HPS) component is a wrapper that interfaces logic in the user design to the
HPS hard logic, simulation models, BFMs, and software handoff files. It instantiates the HPS hard logic in
the user design; and enables other soft components to interface with the HPS hard logic. The HPS
component itself has a small footprint in the FPGA fabric, because its only purpose is to enable soft logic
to connect to the extensive hard logic in the HPS. You can connect soft logic to the HPS.
After the soft logic is connected to the HPS, Qsys ensures the following features:
• Interoperability by adapting Avalon Memory-Mapped (Avalon-MM) interfaces to AXI
• Handle data width mismatches
• Clock domain transfer crossing
This allows you to integrate IP from Altera, 3rd party IP cores, and custom IP cores to the HPS without
having to create integration logic.
For a description of the HPS and its integration into the system on a chip (SoC), refer to the Cyclone V
Device Datasheet.
For a description of the HPS system architecture and features, refer to the "Introduction to the Hard
Processor" and the CoreSight Debug and Trace chapters in volume 3 of the Cyclone V Device Handbook.
For more information about instantiating the HPS component, refer to the Instantiating the HPS
Component chapter in the Hard Processor System Technical Reference Manual.
For more information about the HPS component interfaces, refer to the HPS Component Interfaces chapter
in the Hard Processor System Technical Reference Manual.
For more information about simulating the HPS component, refer to the Simulating the HPS Component
chapter in the Hard Processor System Technical Reference Manual.
Related Information
Cyclone V Device Datasheet
•
• Simulating the HPS Component
HPS Component Interfaces
•
Instantiating the HPS Component
•
Introduction to the Hard Processor System
•
• CoreSight Debug and Trace
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Introduction to the HPS Component

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