Dma Peripheral Request - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Related Information
• Using the Address Span Extender Component
Address span extender details
SDRAM Controller Subsystem
•

DMA Peripheral Request

You can enable each direct memory access (DMA) controller peripheral request ID individually. Each
request ID enables an interface for FPGA soft logic to request one of eight logical DMA channels to the
FPGA.
Related Information
DMA Controller
For more information, refer to the DMA Controller chapter in the Cyclone V Device Handbook, Volume 3 .
Interrupts
Table 27-4: FPGA-to-HPS Interrupts Interface
Parameter Name
Enable FPGA-to-HPS Interrupts
You can enable the interfaces for each HPS peripheral interrupt to the FPGA.
Table 27-5: HPS-to-FPGA Interrupts Interface
The following table lists the available HPS-to-FPGA interrupt interfaces and the corresponding
parameters to enable them.
Parameter Name
Enable CAN interrupts
Enable clock peripheral interrupts
Enable CTI interrupts
Instantiating the HPS Component
Send Feedback
on page 11-1
on page 16-1
Parameter Description
Enables the interface for
FPGA interrupt signals to
the MPU (in the HPS).
Parameter Description
Enables the interface for
HPS CAN controllers
interrupt to the FPGA
Enables the interface for
HPS clock manager and
MPU wake-up interrupt
signals to the FPGA
Enables the interface for
HPS cross-trigger
interrupt signals to the
FPGA
DMA Peripheral Request
on page 27-15
f2h_irq0
f2h_irq1
h2f_can0_interrupt
h2f_can1_interrupt
h2f_clkmgr_interrupt
h2f_mpuwakeup_interrupt
h2f_cti_interrupt0
h2f_cti_interrupt1
27-5
Interface Name
Interface Name
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