Axi Bridges - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Parameter Name
Enable OSC timer interrupts
Enable Quad SPI interrupts
Enable SD/MMC interrupts
Enable SPI master interrupts
Enable SPI slave interrupts
Enable UART interrupts
Enable USB interrupts
Enable watchdog interrupts

AXI Bridges

Table 27-6: Bridge Parameters
Parameter Name
FPGA-to-HPS interface width
Instantiating the HPS Component
Send Feedback
Parameter Description
Enables interface for the
HPS OSC timer interrupt
to the FPGA. For more
information, refer to the
Timer Clock
Characteristics table in the
Timer chapter in the
Cyclone V Device
Handbook, Volume 3.
Enables interface for the
HPS QSPI controller
interrupt to the FPGA
Enables the interface for
the HPS SD/MMC
controller interrupt to the
FPGA
Enables the interface for
the HPS SPI master
controller interrupt to the
FPGA
Enablesthe interface for
the HPS SPI slave
controller interrupt to the
FPGA
Enables the interface for
the HPS UART controller
interrupt to the FPGA
Enables the interface for
the HPS USB controller
interrupt to the FPGA
Enables the interface for
the HPS watchdog
interrupt to the FPGA
Parameter Description
Enable or disable the FPGA-to-HPS
interface; if enabled, set the data
width to 32, 64, or 128 bits.
AXI Bridges
Interface Name
h2f_osc0_interrupt
h2f_osc1_interrupt
h2f_qspi_interrupt
h2f_sdmmc_interrupt
h2f_spi0_interrupt
h2f_spi1_interrupt
h2f_spi2_interrupt
h2f_spi3_interrupt
h2f_uart0_interrupt
h2f_uart1_interrupt
h2f_usb0_interrupt
h2f_usb1_interrupt
h2f_wdog0_interrupt
h2f_wdog1_interrupt
Interface Name
f2h_axi_slave
f2h_axi_clock
27-7
Altera Corporation